2.1 FEATURES
Single ended interface for data, address and command
Quarter data‐rate differential clock inputs CK/CK# for ADR/CMD
Two half data‐rate differential clock inputs WCK/WCK#, each associated with two data bytes (DQ, DBI#, EDC)
Double Data Rate (DDR) data (WCK)
Single Data Rate (SDR) command (CK)
Double Data Rate (DDR) addressing (CK)
8 or 16 internal banks
4 bank groups for tCCDL = 3 tCK and 4 tCK 8n prefetch architecture: 256 bit per array read or write access
Burst length: 8 only
Programmable CAS latency: 5 to 36 tCK Programmable WRITE latency: 1 to 7 tCK WRITE Data mask function via address bus (single/double byte mask)
Data bus inversion (DBI) & address bus inversion (ABI)
Input/output PLL/DLL on/off mode
Address training: address input monitoring by DQ pins
WCK2CK clock training with phase information by EDC pins
Data read and write training via READ FIFO
READ FIFO pattern preload by LDFF command
Direct write data load to READ FIFO by WRTR command
Consecutive read of READ FIFO by RDTR command
Read/Write data transmission integrity secured by cyclic redundancy check (CRC‐8)
READ/WRITE EDC on/off mode
Programmable EDC hold pattern for CDR
Programmable CRC READ latency = 0 to 3 tCK Programmable CRC WRITE latency = 7 to 14 tCK Low Power modes
RDQS mode on EDC pin
Optional on‐chip temperature sensor with read‐out
Auto & self refresh modes
Auto precharge option for each burst access
32ms, auto refresh (8k cycles)
Temperature sensor controlled self refresh rate
Optional digital tRAS lockout
On‐die termination (ODT); nominal values of 60 ohm and 120 ohm
Pseudo open drain (POD‐15) compatible outputs (40 ohm pulldown, 60 ohm pullup)
ODT and output drive strength auto‐calibration with external resistor ZQ pin (120 ohm)
Programmable termination and driver strength offsets
Selectable external or internal VREF for data inputs; programmable offsets for internal VREF
Separate external VREF for address / command inputs
Vendor ID, FIFO depth and Density info fields for identification
x32/x16 mode configuration set at power‐up with EDC pin
Mirror function with MF pin
Boundary scan function with SEN pin
1.5V +/‐ 0.045V supply for device operation (VDD)
1.5V +/‐ 0.045V supply for I/O interface (VDDQ)
170 ball BGA package
