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[Werewolf Jones]

Just waves and waves of specs threads. Fucking hell lad no wonder there's so many gaming side refugees who come to OT. Anyway, what's good GAF?

 

[Phunkydiabetic]

SOMEBODY didn't get a launch consoleeeee

 

[-Arcadia-]

Yeah, not Neogaf specifically, but gaming discussion everywhere seems in a weird place. You’d think we were all more computer graphics enthusiasts than people who actually enjoy games. Then there’s the people trying to out-advertise each other.

Not a lot of actual game discussion at a glance. I need to take a closer look. I know there definitely hasn’t been for the last year.

 

[bender]

Central processing unit

Emotion Engine CPU as found in the SCPH-7000x

The combined EE+GS+RDRAM+DRAM found in the SCPH-7900x and SCPH-9000x series

The ASIC from the SCPH-90001 (CXD2976GB) shaven down to show the EE+GS+RDRAM+DRAM silicon
CPU: MIPS III R5900-based "Emotion Engine", clocked at 294.912 MHz (299 MHz on newer versions), with 128-bit SIMD capabilities[4][5]
250-nm CMOS manufacturing (ending with 65-nm CMOS), 13.5 million transistors, 225 mm² die size,[6] 15 W dissipation (combined EE+GS in SCPH-7500x and later SCPH-7000x): 86 mm², 53.5 million transistors)[7] (combined EE+GS+RDRAM+DRAM in SCPH-7900x ended with 65 nm CMOS design)[8]
CPU core: MIPS R5900 (COP0), 64-bit, little endian (mipsel). CPU is a superscalar, in-order 2-issue design with 6-stage long integer pipelines, 32 32-bit GPR registers, 32 128-bit SIMD linear scalar registers, two 64-bit integer ALUs, 128-bit load-store unit (LSU) and a branch execution unit (BXU).
Instruction set: MIPS III, MIPS IV subset with Sony's proprietary 107 vector SIMD multimedia instructions (MMI). The custom instruction set was implemented by grouping the two 64-bit integer ALUs.
32-bit FPU coprocessor (COP1) with 6-stage long pipeline (floating point multiply accumulator × 1, floating point divider × 1). FPU is not IEEE compliant.
32-bit VLIW-SIMD vector units at 147.456 MHz: VPU0 and VPU1 (floating point multiply accumulator × 9, floating point divider × 1) each VPU contains a vector unit (VU), instruction cache, data cache and interface unit. Each vector unit also has upper execution unit containing 4 × FMAC and lower execution unit containing FDIV, integer ALU, load-store unit, branch logic, 16 16-bit integer registers and 32 128-bit floating point registers. VPU1 has an additional EFU unit.
VPU0 (COP2; FMAC × 4, FDIV × 1) is tightly coupled with the main CPU and is typically used for polygon and geometry transformations (under parallel or serial connection), physics and other gameplay related tasks
VPU1 (Elementary Functional Unit, EFU; FMAC × 5, FDIV × 2) operates independently controlled by microcode, parallel to the CPU core, is typically used for polygon and geometry transformations, clipping, culling, lighting and other visual based calculations (texture matrix able for 2 coordinates (UV/ST))[9]
Parallel: results of VU0/FPU sent as another display list via MFIFO (for e.g. complex characters/vehicles/etc.)
Serial: results of VU0/FPU sent to VU1 (via 3 methods) and can act as an optional geometry pre-processor that does all base work to update the scene every frame (for e.g. camera, perspective, boning and laws of movement such as animations or physics)[10]
Image Processing Unit (IPU): MPEG-2 compressed image macroblock layer decoder allowing playback of DVDs and game FMV. It also allowed vector quantization for 2D graphics data.[11]
Memory management unit (MMU),[12] RDRAM controller and DMA controller: handle memory access within the system
Cache memory: 16 KB instruction cache, 8 KB + 16 KB scratchpad (ScrP) data cache
Scratchpad (SPR) is extended area of memory visible to the EE CPU. This extended memory provides 16 kilobytes of fast RAM available to be used by the application. Scratchpad memory can be used to store temporary data that is waiting to be sent via DMA or for any other temporary storage that the programmer can define.
Interfaces
I/O processor interconnection: remote procedure call over a serial link, DMA controller for bulk transfer
Main RDRAM memory bus. Bandwidth: 3.2 GB/s
Graphics interface (GIF), DMA channel that connects the EE CPU to the GS co-processor. To draw something to the screen, one must send render commands to the GS via the GIF channel: 64-bit, 150 MHz bus, maximum theoretical bandwidth of 1.2 GB/s.[6]
Display lists generated by CPU/VPU0 and VPU1 are sent to the GIF, which prioritizes them before dispatching them to the Graphics Synthesizer for rendering.
Vector Unit Interface (VIF), consists of two DMA channels VIF0 for VPU0 and VIF1 for VPU1. Vector units and the main CPU communicate via VIF DMA channels.
SIF – Serial Interface or Subsystem Interface which consists of 3 DMA channels:
Subsystem Interface 0 (SIF0) and Subsystem Interface 1 (SIF1), used for communication between the EE main CPU and IOP co-processor. These are serial DMA channels where both CPUs can send commands and establish communication through an RPC protocol.
Subsystem Interface 2 (SIF2), used for backwards compatibility with PS1 games and debugging.
Performance
Floating point performance: 6.2 GFLOPS (single precision 32-bit floating point)
FPU 0.64 GFLOPS
VU0 2.44 GFLOPS[13][14]
VU1 3.08 GFLOPS (Including internal 0.64 GFLOPS EFU)
Tri-strip geometric transformation (VU0+VU1): 150 million vertices per second[15]
3D CG geometric transformation with raw 3D perspective operations (VU0+VU1): 66–80+ million vertices per second[9]
3D CG geometric transformations at peak bones/movements/effects (textures)/lights (VU0+VU1, parallel or series): 15–20 million vertices per second[15]
Lighting: 38 million polygons/second
Fog: 36 million polygons/second
Curved surface generation (Bezier): 16 million polygons/second
Image processing performance: 150 million pixels/second
Actual real-world polygons (per frame): 500–650k at 30 FPS, 250–325k at 60 FPS
Instructions per second: 6,000 MIPS (million instructions per second)[16]
System memory
Main memory: 32 MB PC800 32-bit dual-channel (2x 16-bit) RDRAM (Direct Rambus DRAM) @ 400 MHz, 3.2 GB/s peak bandwidth[6]
Graphics processing unit
Parallel rendering processor with embedded DRAM "Graphics Synthesizer" (GS) clocked at 147.456 MHz
279 mm² die (combined EE+GS in SCPH-7500x: 86 mm², 53.5 million transistors)
Programmable CRT controller (PCRTC) for output
Pixel pipelines: 16 without any texture mapping units (TMU), however half of pixel pipelines can perform texturing, so fillrate is either 16 pixels per clock with untextured 2400 Mpixels; or 8 pixels per clock with 1200 megapixels with bilinear texturing, and 1200 megatexels (bilinear).
Video output resolution: Variable from 256×224 to 1920×1080[17]
4 MB of embedded DRAM as video memory (an additional 32 MB of main memory can be used as video memory for off-screen textures); 48 gigabytes per second peak bandwidth
Texture buffer bandwidth: 9.6 GB/s
Frame buffer bandwidth: 38.4 GB/s
eDRAM bus width: 2560-bit (composed of three independent buses: 1024-bit write, 1024-bit read, 512-bit read/write)
Pixel configuration: RGB:alpha, 24:8, 15:1; 16-, 24-, or 32-bit Z-buffer
Display color depth: 32-bit (RGBA: 8 bits each)
Dedicated connection to main CPU and VU1
Overall pixel fillrate: 16 × 147 Mpix/s = 2.352 gigapixel/s
1.2 gigapixel/s (with Z-buffer, alpha, and texture)
With no texture, flat shaded: 2.4 Gpix/s (75,000,000 32-pixel raster triangles)
With 1 full texture (diffuse map), Gouraud shaded: 1.2 Gpix/s (37,750,000 32-bit pixel raster triangles)
With 2 full textures (diffuse map and specular, alpha, or other), Gouraud shaded: 0.6 Gpix/s (18,750,000 32-bit pixel raster triangles)
Texture fillrate: 1.2 Gtexel/s
Sprite drawing rate: 18.75 million/s (8×8 pixels)
Particle drawing rate: 150 million/s
Polygon drawing rate: 75 million/s (small polygon)
50 million/s (48-pixel quad with Z and A)
30 million/s (50-pixel triangle with Z and A)
25 million/s (48-pixel quad with Z, A and T)
16 million/s (75-pixel triangle with Z, A, T and fog)[18]
VESA (maximum 1280×1024 pixels)
3 rendering paths (path 1, 2 and 3)

Graphics Synthesizer as found in SCPH-390xx
GS effects include: read-write textures, emboss bump mapping, Dot3 bump mapping (normal mapping),[19] multiple-light sources, per-vertex lighting, volumetric fog, mipmapping, LOD, spherical harmonic lighting,[20] high dynamic range (HDR) rendering, motion blur, heat haze, bloom, depth of field, shadow volumes, shadow mapping, lightmapping, environment mapping, render-to-texture, alpha blending, alpha test, destination alpha test, depth test, scissor test, transparency effects, framebuffer effects, post-processing effects, perspective-correct texture mapping, edge-AAx2 (poly sorting required),[9] bilinear, trilinear texture filtering, multi-pass, palletizing (6:1 ratio 4-bit; 3:1 ratio 8-bit), NURBS, Bezier curves, Bezier surfaces, B-splines, offscreen drawing, framebuffer mask, flat shading, Gouraud shading, cel shading, dithering, texture swizzling.
Multi-pass rendering ability
Four passes: 300 Mpixel/s (300 Mpixels/s divided by 32 pixels = 9,375,000 triangles/s lost every four passes)[21]
Audio
Audio: "SPU1+SPU2" (SPU1 is actually the CPU clocked at 8 MHz and SPU2 is PS1 SPU)
Sound Memory: 2 MB
Number of voices: 48 hardware channels of ADPCM on SPU2 plus software-mixed definable, programmable channels
Sampling Frequency: 44.1 kHz or 48 kHz (selectable)
PCM audio source
Digital effects include:
Pitch Modulation
Envelope
Looping
Digital Reverb
Load up to 512K of sampled waveforms
Supports MIDI Instruments
Output: Dolby Digital 5.1 Surround sound, DTS (Full motion video only), later games achieved matrix encoded 5.1 surround during gameplay through Dolby Pro Logic II
I/O processor
Input Output Processor (IOP)
I/O Memory: 2 MB EDO DRAM
CPU Core: Original PlayStation CPU (MIPS R3000A clocked at 33.8688 MHz or 37.5 MHz+PS1 GTE and MDEC for backwards compatibility with PS1 games)
Automatically underclocked to 33.8688 MHz to achieve hardware backwards compatibility with original PlayStation format games.
Sub Bus: 32-bit
Connection to: SPU and CD/DVD controller.
Replaced with PowerPC-based "Deckard" IOP with 4 MB SDRAM starting with SCPH-7500x.

Connectivity
2 proprietary PlayStation controller ports (250 kHz clock for PS1 and 500 kHz for PS2 controllers)
2 proprietary Memory Card slots using MagicGate encryption (250 kHz for PS1 cards. Up to 2 MHz for PS2 cards with an average sequential read/write speed of 130 kbit/s)
2 USB 1.1 ports with an OHCI-compatible controller
AV Multi Out (Composite video, S-Video, RGBS (SCART), RGsB (VGA connector†), YPBPR (component), and D-Terminal)
RFU DC Out
S/PDIF Digital Out
Expansion Bay for 3.5-inch HDD and Network Adaptor (required for HDD, SCPH-300xx to 500xx only)[22]
PC Card slot for Network Adaptor (PC Card type) and External Hard Disk Drive (SCPH-10000, SCPH-15000, SCPH-18000 models)[23]
Emotion Engine (EE) includes an on-chip Serial I/O port(SIO) used internally by the EE's kernel to output debugging and messages and to start the kernel debugger.
Ethernet port (Slim only)
i.LINK (also known as FireWire) (SCPH-10000 to 3900x only)[24]
Infrared remote control port (SCPH-500xx and newer)[25]
^† VGA connector is only available for progressive-scan supporting games, homebrew-enabled systems, and Linux for PlayStation 2, and requires a monitor that supports RGsB, or "sync on green," signals.

Optical disc drive
Disc Drive type: proprietary interface through a custom micro-controller + DSP chip. 24x speed CD-ROM [3.6 MB/s], 4x speed DVD-ROM [5.28 MB/s] — region-locked with copy protection.
Supported Disc Media: PlayStation 2 format CD-ROM, PlayStation format CD-ROM, CD-DA, PlayStation 2 format DVD-ROM, DVD Video. DVD5 (Single-layer, 4.7 GB) and DVD9 (Dual-layer, 8.5 GB) supported. Later models starting with SCPH-500xx are DVD+RW and DVD-RW compatible.

 

[Slings and Arrows]

I think it's because of how the consoles have launched this year. Covid excuses aside, there are very few, if any, next gen games. Add to that no midnight launches, no hype, very limited stock...

Those who have a console will be 'playing it', those who don't will be F5'ing the shit out of Amazon.

 

[teezzy]

Yeah, not Neogaf specifically, but gaming discussion everywhere seems in a weird place. You’d think we were all more computer graphics enthusiasts than people who actually enjoy games. Then there’s the people trying to out-advertise each other.

Not a lot of actual game discussion at a glance. I need to take a closer look. I know there definitely hasn’t been for the last year.

You discuss games elsewhere?

 

[T8SC]

Same shit, different generation.

 

[-Arcadia-]

You discuss games elsewhere?

I would never cheat on NeoGaf. (Slaps you)

I do glance in whenever there’s an interesting comment section or an event, or just watch lots of Series X/PS5 videos and my impression is that it’s all visuals, specs, and fighting over the best one.

 

[Tesseract]

Central processing unit

Emotion Engine CPU as found in the SCPH-7000x

The combined EE+GS+RDRAM+DRAM found in the SCPH-7900x and SCPH-9000x series

The ASIC from the SCPH-90001 (CXD2976GB) shaven down to show the EE+GS+RDRAM+DRAM silicon
CPU: MIPS III R5900-based "Emotion Engine", clocked at 294.912 MHz (299 MHz on newer versions), with 128-bit SIMD capabilities[4][5]
250-nm CMOS manufacturing (ending with 65-nm CMOS), 13.5 million transistors, 225 mm² die size,[6] 15 W dissipation (combined EE+GS in SCPH-7500x and later SCPH-7000x): 86 mm², 53.5 million transistors)[7] (combined EE+GS+RDRAM+DRAM in SCPH-7900x ended with 65 nm CMOS design)[8]
CPU core: MIPS R5900 (COP0), 64-bit, little endian (mipsel). CPU is a superscalar, in-order 2-issue design with 6-stage long integer pipelines, 32 32-bit GPR registers, 32 128-bit SIMD linear scalar registers, two 64-bit integer ALUs, 128-bit load-store unit (LSU) and a branch execution unit (BXU).
Instruction set: MIPS III, MIPS IV subset with Sony's proprietary 107 vector SIMD multimedia instructions (MMI). The custom instruction set was implemented by grouping the two 64-bit integer ALUs.
32-bit FPU coprocessor (COP1) with 6-stage long pipeline (floating point multiply accumulator × 1, floating point divider × 1). FPU is not IEEE compliant.
32-bit VLIW-SIMD vector units at 147.456 MHz: VPU0 and VPU1 (floating point multiply accumulator × 9, floating point divider × 1) each VPU contains a vector unit (VU), instruction cache, data cache and interface unit. Each vector unit also has upper execution unit containing 4 × FMAC and lower execution unit containing FDIV, integer ALU, load-store unit, branch logic, 16 16-bit integer registers and 32 128-bit floating point registers. VPU1 has an additional EFU unit.
VPU0 (COP2; FMAC × 4, FDIV × 1) is tightly coupled with the main CPU and is typically used for polygon and geometry transformations (under parallel or serial connection), physics and other gameplay related tasks
VPU1 (Elementary Functional Unit, EFU; FMAC × 5, FDIV × 2) operates independently controlled by microcode, parallel to the CPU core, is typically used for polygon and geometry transformations, clipping, culling, lighting and other visual based calculations (texture matrix able for 2 coordinates (UV/ST))[9]
Parallel: results of VU0/FPU sent as another display list via MFIFO (for e.g. complex characters/vehicles/etc.)
Serial: results of VU0/FPU sent to VU1 (via 3 methods) and can act as an optional geometry pre-processor that does all base work to update the scene every frame (for e.g. camera, perspective, boning and laws of movement such as animations or physics)[10]
Image Processing Unit (IPU): MPEG-2 compressed image macroblock layer decoder allowing playback of DVDs and game FMV. It also allowed vector quantization for 2D graphics data.[11]
Memory management unit (MMU),[12] RDRAM controller and DMA controller: handle memory access within the system
Cache memory: 16 KB instruction cache, 8 KB + 16 KB scratchpad (ScrP) data cache
Scratchpad (SPR) is extended area of memory visible to the EE CPU. This extended memory provides 16 kilobytes of fast RAM available to be used by the application. Scratchpad memory can be used to store temporary data that is waiting to be sent via DMA or for any other temporary storage that the programmer can define.
Interfaces
I/O processor interconnection: remote procedure call over a serial link, DMA controller for bulk transfer
Main RDRAM memory bus. Bandwidth: 3.2 GB/s
Graphics interface (GIF), DMA channel that connects the EE CPU to the GS co-processor. To draw something to the screen, one must send render commands to the GS via the GIF channel: 64-bit, 150 MHz bus, maximum theoretical bandwidth of 1.2 GB/s.[6]
Display lists generated by CPU/VPU0 and VPU1 are sent to the GIF, which prioritizes them before dispatching them to the Graphics Synthesizer for rendering.
Vector Unit Interface (VIF), consists of two DMA channels VIF0 for VPU0 and VIF1 for VPU1. Vector units and the main CPU communicate via VIF DMA channels.
SIF – Serial Interface or Subsystem Interface which consists of 3 DMA channels:
Subsystem Interface 0 (SIF0) and Subsystem Interface 1 (SIF1), used for communication between the EE main CPU and IOP co-processor. These are serial DMA channels where both CPUs can send commands and establish communication through an RPC protocol.
Subsystem Interface 2 (SIF2), used for backwards compatibility with PS1 games and debugging.
Performance
Floating point performance: 6.2 GFLOPS (single precision 32-bit floating point)
FPU 0.64 GFLOPS
VU0 2.44 GFLOPS[13][14]
VU1 3.08 GFLOPS (Including internal 0.64 GFLOPS EFU)
Tri-strip geometric transformation (VU0+VU1): 150 million vertices per second[15]
3D CG geometric transformation with raw 3D perspective operations (VU0+VU1): 66–80+ million vertices per second[9]
3D CG geometric transformations at peak bones/movements/effects (textures)/lights (VU0+VU1, parallel or series): 15–20 million vertices per second[15]
Lighting: 38 million polygons/second
Fog: 36 million polygons/second
Curved surface generation (Bezier): 16 million polygons/second
Image processing performance: 150 million pixels/second
Actual real-world polygons (per frame): 500–650k at 30 FPS, 250–325k at 60 FPS
Instructions per second: 6,000 MIPS (million instructions per second)[16]
System memory
Main memory: 32 MB PC800 32-bit dual-channel (2x 16-bit) RDRAM (Direct Rambus DRAM) @ 400 MHz, 3.2 GB/s peak bandwidth[6]
Graphics processing unit
Parallel rendering processor with embedded DRAM "Graphics Synthesizer" (GS) clocked at 147.456 MHz
279 mm² die (combined EE+GS in SCPH-7500x: 86 mm², 53.5 million transistors)
Programmable CRT controller (PCRTC) for output
Pixel pipelines: 16 without any texture mapping units (TMU), however half of pixel pipelines can perform texturing, so fillrate is either 16 pixels per clock with untextured 2400 Mpixels; or 8 pixels per clock with 1200 megapixels with bilinear texturing, and 1200 megatexels (bilinear).
Video output resolution: Variable from 256×224 to 1920×1080[17]
4 MB of embedded DRAM as video memory (an additional 32 MB of main memory can be used as video memory for off-screen textures); 48 gigabytes per second peak bandwidth
Texture buffer bandwidth: 9.6 GB/s
Frame buffer bandwidth: 38.4 GB/s
eDRAM bus width: 2560-bit (composed of three independent buses: 1024-bit write, 1024-bit read, 512-bit read/write)
Pixel configuration: RGB:alpha, 24:8, 15:1; 16-, 24-, or 32-bit Z-buffer
Display color depth: 32-bit (RGBA: 8 bits each)
Dedicated connection to main CPU and VU1
Overall pixel fillrate: 16 × 147 Mpix/s = 2.352 gigapixel/s
1.2 gigapixel/s (with Z-buffer, alpha, and texture)
With no texture, flat shaded: 2.4 Gpix/s (75,000,000 32-pixel raster triangles)
With 1 full texture (diffuse map), Gouraud shaded: 1.2 Gpix/s (37,750,000 32-bit pixel raster triangles)
With 2 full textures (diffuse map and specular, alpha, or other), Gouraud shaded: 0.6 Gpix/s (18,750,000 32-bit pixel raster triangles)
Texture fillrate: 1.2 Gtexel/s
Sprite drawing rate: 18.75 million/s (8×8 pixels)
Particle drawing rate: 150 million/s
Polygon drawing rate: 75 million/s (small polygon)
50 million/s (48-pixel quad with Z and A)
30 million/s (50-pixel triangle with Z and A)
25 million/s (48-pixel quad with Z, A and T)
16 million/s (75-pixel triangle with Z, A, T and fog)[18]
VESA (maximum 1280×1024 pixels)
3 rendering paths (path 1, 2 and 3)

Graphics Synthesizer as found in SCPH-390xx
GS effects include: read-write textures, emboss bump mapping, Dot3 bump mapping (normal mapping),[19] multiple-light sources, per-vertex lighting, volumetric fog, mipmapping, LOD, spherical harmonic lighting,[20] high dynamic range (HDR) rendering, motion blur, heat haze, bloom, depth of field, shadow volumes, shadow mapping, lightmapping, environment mapping, render-to-texture, alpha blending, alpha test, destination alpha test, depth test, scissor test, transparency effects, framebuffer effects, post-processing effects, perspective-correct texture mapping, edge-AAx2 (poly sorting required),[9] bilinear, trilinear texture filtering, multi-pass, palletizing (6:1 ratio 4-bit; 3:1 ratio 8-bit), NURBS, Bezier curves, Bezier surfaces, B-splines, offscreen drawing, framebuffer mask, flat shading, Gouraud shading, cel shading, dithering, texture swizzling.
Multi-pass rendering ability
Four passes: 300 Mpixel/s (300 Mpixels/s divided by 32 pixels = 9,375,000 triangles/s lost every four passes)[21]
Audio
Audio: "SPU1+SPU2" (SPU1 is actually the CPU clocked at 8 MHz and SPU2 is PS1 SPU)
Sound Memory: 2 MB
Number of voices: 48 hardware channels of ADPCM on SPU2 plus software-mixed definable, programmable channels
Sampling Frequency: 44.1 kHz or 48 kHz (selectable)
PCM audio source
Digital effects include:
Pitch Modulation
Envelope
Looping
Digital Reverb
Load up to 512K of sampled waveforms
Supports MIDI Instruments
Output: Dolby Digital 5.1 Surround sound, DTS (Full motion video only), later games achieved matrix encoded 5.1 surround during gameplay through Dolby Pro Logic II
I/O processor
Input Output Processor (IOP)
I/O Memory: 2 MB EDO DRAM
CPU Core: Original PlayStation CPU (MIPS R3000A clocked at 33.8688 MHz or 37.5 MHz+PS1 GTE and MDEC for backwards compatibility with PS1 games)
Automatically underclocked to 33.8688 MHz to achieve hardware backwards compatibility with original PlayStation format games.
Sub Bus: 32-bit
Connection to: SPU and CD/DVD controller.
Replaced with PowerPC-based "Deckard" IOP with 4 MB SDRAM starting with SCPH-7500x.

Connectivity
2 proprietary PlayStation controller ports (250 kHz clock for PS1 and 500 kHz for PS2 controllers)
2 proprietary Memory Card slots using MagicGate encryption (250 kHz for PS1 cards. Up to 2 MHz for PS2 cards with an average sequential read/write speed of 130 kbit/s)
2 USB 1.1 ports with an OHCI-compatible controller
AV Multi Out (Composite video, S-Video, RGBS (SCART), RGsB (VGA connector†), YPBPR (component), and D-Terminal)
RFU DC Out
S/PDIF Digital Out
Expansion Bay for 3.5-inch HDD and Network Adaptor (required for HDD, SCPH-300xx to 500xx only)[22]
PC Card slot for Network Adaptor (PC Card type) and External Hard Disk Drive (SCPH-10000, SCPH-15000, SCPH-18000 models)[23]
Emotion Engine (EE) includes an on-chip Serial I/O port(SIO) used internally by the EE's kernel to output debugging and messages and to start the kernel debugger.
Ethernet port (Slim only)
i.LINK (also known as FireWire) (SCPH-10000 to 3900x only)[24]
Infrared remote control port (SCPH-500xx and newer)[25]
^† VGA connector is only available for progressive-scan supporting games, homebrew-enabled systems, and Linux for PlayStation 2, and requires a monitor that supports RGsB, or "sync on green," signals.

Optical disc drive
Disc Drive type: proprietary interface through a custom micro-controller + DSP chip. 24x speed CD-ROM [3.6 MB/s], 4x speed DVD-ROM [5.28 MB/s] — region-locked with copy protection.
Supported Disc Media: PlayStation 2 format CD-ROM, PlayStation format CD-ROM, CD-DA, PlayStation 2 format DVD-ROM, DVD Video. DVD5 (Single-layer, 4.7 GB) and DVD9 (Dual-layer, 8.5 GB) supported. Later models starting with SCPH-500xx are DVD+RW and DVD-RW compatible.

 

[EverydayBeast]

Hype fatigue will kick in no way they maintain that level of hype

 

[SLoWMoTIoN]

Central processing unit

Emotion Engine CPU as found in the SCPH-7000x

The combined EE+GS+RDRAM+DRAM found in the SCPH-7900x and SCPH-9000x series

The ASIC from the SCPH-90001 (CXD2976GB) shaven down to show the EE+GS+RDRAM+DRAM silicon
CPU: MIPS III R5900-based "Emotion Engine", clocked at 294.912 MHz (299 MHz on newer versions), with 128-bit SIMD capabilities[4][5]
250-nm CMOS manufacturing (ending with 65-nm CMOS), 13.5 million transistors, 225 mm² die size,[6] 15 W dissipation (combined EE+GS in SCPH-7500x and later SCPH-7000x): 86 mm², 53.5 million transistors)[7] (combined EE+GS+RDRAM+DRAM in SCPH-7900x ended with 65 nm CMOS design)[8]
CPU core: MIPS R5900 (COP0), 64-bit, little endian (mipsel). CPU is a superscalar, in-order 2-issue design with 6-stage long integer pipelines, 32 32-bit GPR registers, 32 128-bit SIMD linear scalar registers, two 64-bit integer ALUs, 128-bit load-store unit (LSU) and a branch execution unit (BXU).
Instruction set: MIPS III, MIPS IV subset with Sony's proprietary 107 vector SIMD multimedia instructions (MMI). The custom instruction set was implemented by grouping the two 64-bit integer ALUs.
32-bit FPU coprocessor (COP1) with 6-stage long pipeline (floating point multiply accumulator × 1, floating point divider × 1). FPU is not IEEE compliant.
32-bit VLIW-SIMD vector units at 147.456 MHz: VPU0 and VPU1 (floating point multiply accumulator × 9, floating point divider × 1) each VPU contains a vector unit (VU), instruction cache, data cache and interface unit. Each vector unit also has upper execution unit containing 4 × FMAC and lower execution unit containing FDIV, integer ALU, load-store unit, branch logic, 16 16-bit integer registers and 32 128-bit floating point registers. VPU1 has an additional EFU unit.
VPU0 (COP2; FMAC × 4, FDIV × 1) is tightly coupled with the main CPU and is typically used for polygon and geometry transformations (under parallel or serial connection), physics and other gameplay related tasks
VPU1 (Elementary Functional Unit, EFU; FMAC × 5, FDIV × 2) operates independently controlled by microcode, parallel to the CPU core, is typically used for polygon and geometry transformations, clipping, culling, lighting and other visual based calculations (texture matrix able for 2 coordinates (UV/ST))[9]
Parallel: results of VU0/FPU sent as another display list via MFIFO (for e.g. complex characters/vehicles/etc.)
Serial: results of VU0/FPU sent to VU1 (via 3 methods) and can act as an optional geometry pre-processor that does all base work to update the scene every frame (for e.g. camera, perspective, boning and laws of movement such as animations or physics)[10]
Image Processing Unit (IPU): MPEG-2 compressed image macroblock layer decoder allowing playback of DVDs and game FMV. It also allowed vector quantization for 2D graphics data.[11]
Memory management unit (MMU),[12] RDRAM controller and DMA controller: handle memory access within the system
Cache memory: 16 KB instruction cache, 8 KB + 16 KB scratchpad (ScrP) data cache
Scratchpad (SPR) is extended area of memory visible to the EE CPU. This extended memory provides 16 kilobytes of fast RAM available to be used by the application. Scratchpad memory can be used to store temporary data that is waiting to be sent via DMA or for any other temporary storage that the programmer can define.
Interfaces
I/O processor interconnection: remote procedure call over a serial link, DMA controller for bulk transfer
Main RDRAM memory bus. Bandwidth: 3.2 GB/s
Graphics interface (GIF), DMA channel that connects the EE CPU to the GS co-processor. To draw something to the screen, one must send render commands to the GS via the GIF channel: 64-bit, 150 MHz bus, maximum theoretical bandwidth of 1.2 GB/s.[6]
Display lists generated by CPU/VPU0 and VPU1 are sent to the GIF, which prioritizes them before dispatching them to the Graphics Synthesizer for rendering.
Vector Unit Interface (VIF), consists of two DMA channels VIF0 for VPU0 and VIF1 for VPU1. Vector units and the main CPU communicate via VIF DMA channels.
SIF – Serial Interface or Subsystem Interface which consists of 3 DMA channels:
Subsystem Interface 0 (SIF0) and Subsystem Interface 1 (SIF1), used for communication between the EE main CPU and IOP co-processor. These are serial DMA channels where both CPUs can send commands and establish communication through an RPC protocol.
Subsystem Interface 2 (SIF2), used for backwards compatibility with PS1 games and debugging.
Performance
Floating point performance: 6.2 GFLOPS (single precision 32-bit floating point)
FPU 0.64 GFLOPS
VU0 2.44 GFLOPS[13][14]
VU1 3.08 GFLOPS (Including internal 0.64 GFLOPS EFU)
Tri-strip geometric transformation (VU0+VU1): 150 million vertices per second[15]
3D CG geometric transformation with raw 3D perspective operations (VU0+VU1): 66–80+ million vertices per second[9]
3D CG geometric transformations at peak bones/movements/effects (textures)/lights (VU0+VU1, parallel or series): 15–20 million vertices per second[15]
Lighting: 38 million polygons/second
Fog: 36 million polygons/second
Curved surface generation (Bezier): 16 million polygons/second
Image processing performance: 150 million pixels/second
Actual real-world polygons (per frame): 500–650k at 30 FPS, 250–325k at 60 FPS
Instructions per second: 6,000 MIPS (million instructions per second)[16]
System memory
Main memory: 32 MB PC800 32-bit dual-channel (2x 16-bit) RDRAM (Direct Rambus DRAM) @ 400 MHz, 3.2 GB/s peak bandwidth[6]
Graphics processing unit
Parallel rendering processor with embedded DRAM "Graphics Synthesizer" (GS) clocked at 147.456 MHz
279 mm² die (combined EE+GS in SCPH-7500x: 86 mm², 53.5 million transistors)
Programmable CRT controller (PCRTC) for output
Pixel pipelines: 16 without any texture mapping units (TMU), however half of pixel pipelines can perform texturing, so fillrate is either 16 pixels per clock with untextured 2400 Mpixels; or 8 pixels per clock with 1200 megapixels with bilinear texturing, and 1200 megatexels (bilinear).
Video output resolution: Variable from 256×224 to 1920×1080[17]
4 MB of embedded DRAM as video memory (an additional 32 MB of main memory can be used as video memory for off-screen textures); 48 gigabytes per second peak bandwidth
Texture buffer bandwidth: 9.6 GB/s
Frame buffer bandwidth: 38.4 GB/s
eDRAM bus width: 2560-bit (composed of three independent buses: 1024-bit write, 1024-bit read, 512-bit read/write)
Pixel configuration: RGB:alpha, 24:8, 15:1; 16-, 24-, or 32-bit Z-buffer
Display color depth: 32-bit (RGBA: 8 bits each)
Dedicated connection to main CPU and VU1
Overall pixel fillrate: 16 × 147 Mpix/s = 2.352 gigapixel/s
1.2 gigapixel/s (with Z-buffer, alpha, and texture)
With no texture, flat shaded: 2.4 Gpix/s (75,000,000 32-pixel raster triangles)
With 1 full texture (diffuse map), Gouraud shaded: 1.2 Gpix/s (37,750,000 32-bit pixel raster triangles)
With 2 full textures (diffuse map and specular, alpha, or other), Gouraud shaded: 0.6 Gpix/s (18,750,000 32-bit pixel raster triangles)
Texture fillrate: 1.2 Gtexel/s
Sprite drawing rate: 18.75 million/s (8×8 pixels)
Particle drawing rate: 150 million/s
Polygon drawing rate: 75 million/s (small polygon)
50 million/s (48-pixel quad with Z and A)
30 million/s (50-pixel triangle with Z and A)
25 million/s (48-pixel quad with Z, A and T)
16 million/s (75-pixel triangle with Z, A, T and fog)[18]
VESA (maximum 1280×1024 pixels)
3 rendering paths (path 1, 2 and 3)

Graphics Synthesizer as found in SCPH-390xx
GS effects include: read-write textures, emboss bump mapping, Dot3 bump mapping (normal mapping),[19] multiple-light sources, per-vertex lighting, volumetric fog, mipmapping, LOD, spherical harmonic lighting,[20] high dynamic range (HDR) rendering, motion blur, heat haze, bloom, depth of field, shadow volumes, shadow mapping, lightmapping, environment mapping, render-to-texture, alpha blending, alpha test, destination alpha test, depth test, scissor test, transparency effects, framebuffer effects, post-processing effects, perspective-correct texture mapping, edge-AAx2 (poly sorting required),[9] bilinear, trilinear texture filtering, multi-pass, palletizing (6:1 ratio 4-bit; 3:1 ratio 8-bit), NURBS, Bezier curves, Bezier surfaces, B-splines, offscreen drawing, framebuffer mask, flat shading, Gouraud shading, cel shading, dithering, texture swizzling.
Multi-pass rendering ability
Four passes: 300 Mpixel/s (300 Mpixels/s divided by 32 pixels = 9,375,000 triangles/s lost every four passes)[21]
Audio
Audio: "SPU1+SPU2" (SPU1 is actually the CPU clocked at 8 MHz and SPU2 is PS1 SPU)
Sound Memory: 2 MB
Number of voices: 48 hardware channels of ADPCM on SPU2 plus software-mixed definable, programmable channels
Sampling Frequency: 44.1 kHz or 48 kHz (selectable)
PCM audio source
Digital effects include:
Pitch Modulation
Envelope
Looping
Digital Reverb
Load up to 512K of sampled waveforms
Supports MIDI Instruments
Output: Dolby Digital 5.1 Surround sound, DTS (Full motion video only), later games achieved matrix encoded 5.1 surround during gameplay through Dolby Pro Logic II
I/O processor
Input Output Processor (IOP)
I/O Memory: 2 MB EDO DRAM
CPU Core: Original PlayStation CPU (MIPS R3000A clocked at 33.8688 MHz or 37.5 MHz+PS1 GTE and MDEC for backwards compatibility with PS1 games)
Automatically underclocked to 33.8688 MHz to achieve hardware backwards compatibility with original PlayStation format games.
Sub Bus: 32-bit
Connection to: SPU and CD/DVD controller.
Replaced with PowerPC-based "Deckard" IOP with 4 MB SDRAM starting with SCPH-7500x.

Connectivity
2 proprietary PlayStation controller ports (250 kHz clock for PS1 and 500 kHz for PS2 controllers)
2 proprietary Memory Card slots using MagicGate encryption (250 kHz for PS1 cards. Up to 2 MHz for PS2 cards with an average sequential read/write speed of 130 kbit/s)
2 USB 1.1 ports with an OHCI-compatible controller
AV Multi Out (Composite video, S-Video, RGBS (SCART), RGsB (VGA connector†), YPBPR (component), and D-Terminal)
RFU DC Out
S/PDIF Digital Out
Expansion Bay for 3.5-inch HDD and Network Adaptor (required for HDD, SCPH-300xx to 500xx only)[22]
PC Card slot for Network Adaptor (PC Card type) and External Hard Disk Drive (SCPH-10000, SCPH-15000, SCPH-18000 models)[23]
Emotion Engine (EE) includes an on-chip Serial I/O port(SIO) used internally by the EE's kernel to output debugging and messages and to start the kernel debugger.
Ethernet port (Slim only)
i.LINK (also known as FireWire) (SCPH-10000 to 3900x only)[24]
Infrared remote control port (SCPH-500xx and newer)[25]
^† VGA connector is only available for progressive-scan supporting games, homebrew-enabled systems, and Linux for PlayStation 2, and requires a monitor that supports RGsB, or "sync on green," signals.

Optical disc drive
Disc Drive type: proprietary interface through a custom micro-controller + DSP chip. 24x speed CD-ROM [3.6 MB/s], 4x speed DVD-ROM [5.28 MB/s] — region-locked with copy protection.
Supported Disc Media: PlayStation 2 format CD-ROM, PlayStation format CD-ROM, CD-DA, PlayStation 2 format DVD-ROM, DVD Video. DVD5 (Single-layer, 4.7 GB) and DVD9 (Dual-layer, 8.5 GB) supported. Later models starting with SCPH-500xx are DVD+RW and DVD-RW compatible.

I'm not reading any of this shit.

 

[Tesseract]

that's why dimensional analysis exists