The SCORPIO architecture is incorporated in an 11 mm-by-
13 mm chip prototype, fabricated in IBM 45nm SOI technology,
comprising 36 Freescale e200 Power ArchitectureTMcores with
private L1 and L2 caches interfacing with the NoC via ARM
AMBA, along with two Cadence on-chip DDR2 controllers.
The chip prototype achieves a post synthesis operating frequency
of 1 GHz (833 MHz post-layout) with an estimated
power of 28.8 W (768 mW per tile), while the network consumes
only 10% of tile area and 19 % of tile power.