thicc_girls_are_teh_best
Member
So I'm finally ready to post my write-ups on mid-gen and next-next gen console speculations. It's a lot, so I'm breaking it down into parts focused on specific systems. And I also tried focusing on the design philosophy of the products keeping in mind the business models Sony and Microsoft seem to be going for. I did a Part 1 here but that was just in trying to figure out PS5 power consumption amounts, mainly on the GPU side. That's something probably worth keeping in mind as the PlayStation-related stuff is touched up on.
I'm starting with the mid-gen refreshes, one system at a time (originally planned to do all three mid-gen refreshes in one thread, but the write-up grew VERY quickly, so better to give each system its own thread), and then I'll get to the next-next gen stuff. I'm also open to ideas on suggestions with tuning some of these specs, since this needn't be an open-and-shut deal. Seeing that the embargos were finally lifted today, let's start with Sony, and the PlayStation 5 Pro...
----------
In my honest opinion, I think market and technology realities are going to be the driving forces behind what goes into the mid-gen refreshes more than anything. That is to say, I personally think anyone hoping for HBM2, super Big Navi-tier GPU upgrades pushing 20 - 30 TF etc., are in for a massive disappointment in that regard. There are no feasible advances in terms of node shrink reductions, surrounding memory technologies (that would be affordable), or pricing for component R&D and system designs that would enable such mid-gen refreshes being a reality........for the MOST part
Due to this, I'm of the personal opinion that the mid-gen refreshes from Sony and Microsoft will focus on the following main goals:
Now then, maybe it's time we move on to giving some system speculations now? Let's go...
[SONY]
Sony's PS5 Pro mid-gen refresh will most likely release in 2023. I see it implementing a chiplet design, not as 2x 36 CU chips, but as 2x 18 CU chiplets, to mimic the base PS5's GPU setup, only without needing four disabled CUs present (on a chiplet design, redundant silicon doesn't need to actually be present on the die). It will be RDNA 4-based, but also take features liberally from the RDNA 5 standard and customize the GPU setup with some of those features. It's very possible Sony would take more from the RDNA 5 spec into their GPU design compared to Microsoft.
Being a chiplet design, we already know the chances are strong that RDNA 3 will be chiplet-based in some capacity. Regardless, I did have my own idea for how a chiplet setup could pan out. On PS5 Pro, each of the two chiplets would feature 18 CUs and 2x 16 ROP/ColorDepth blocks (32 ROPs per chiplet).
To network the two chiplet in tandem, some of the typical GPU logic would need to be split off onto smaller complementary chiplets. One of these would be the "Unifying GPU Chiplet", or UGC for short. The UGC would handle a bevy of things. Chiefly:
The other big complementary GPU chiplet component in the PS5 Pro would be the Unifying Framebuffer Chiplet block, which can be called the UFC for short. This would house the Display block typically seen in AMD GPUs, among some other things, and likely include some various combine modes for dual framebuffers (for the two GPU chiplets) that could selected as presets by developers depending on what type of rendering pipeline they'd wish to utilize for their game. You can think of these various rendering display preset combinations for the dual framebuffers as a mix of the SEGA Saturn's dual framebuffers and the SNES's various Mode settings (such as Mode 7).
The goal here, though, would be to have programming complexity reduced simply to the developer selecting a combination mode for the two framebuffers as long as they understand how the modes function the hardware itself should do the heavy lifting in combining and sorting the stitched outputs depending on what the game wants, and the combination modes should also be able to be switched between 1-2 cycles, to mix combination modes on the needs of what the game needs for optimal output. This is key for allowing maximized use of the framebuffer capabilities, but it also means the UFC needs to have these different framebuffer combination preset modes readily accessible on some type of private local memory. It's best to picture it, then, as an advanced VDP (Video Display Processor); some chunk of NOR flash and embedded SRAM cache in the UFC would be best for this (the NOR flash could store the presets and even allow for XIP (Execute In Place) if desired, while the SRAM would be for fast memory; some hierarchy of L0$, L1$ and L2$ is probably best).
Aside from the aforementioned GPU talk, a PS5 Pro would likely see improved support for PSVR2, with some bump in the Wifi 6 standard. For wired and perhaps wireless dongle-based PSVR connectivity, there could also be a Thuderbolt port provided via supercharging the USB-C port. The last big technological push I could see for a PS5 Pro is inclusion of persistent memory. Sony actually have some patents for ReRAM, which can potentially be used as both a storage-class and DRAM-like class memory technology. By the time a PS5 Pro would be ready, I think Sony would at least have storage-class ReRAM ready. The goal of it would be similar to the role Optane memory serves on compliant desktop PCs; as a bridge between storage-class memory and system RAM.
A block of 32 GB of ReRAM developed in-house (and likely manufactured/fabbed by Sony via TSMC) would be able to provide a notable performance boost to data I/O on a PS5 Pro while having much lower latency than NAND, support for smaller granularity levels in block data sizes, much higher endurance P/E cycles, and more bandwidth compared to even high-class SSDs on the market. While there is currently no commercial ReRAM on the market, there is at least one company with an IP license for storage-class ReRAM providing 25 GB/s of bandwidth. By the time of a PS5 Pro, especially if the ReRA itself had time to mature in the commercial market from 2021 or even 2022 and onward, Sony could possibly have a 24 GB/s - 25 GB/s bandwidth ReRAM solution that could be implemented in a mid-gen refresh at an affordable rate, serving as a great starting ground for similar technology in a PS6.
Due to this, however, I actually DON'T see them doing too much with an SSD I/O spec bump. While the SSD size will likely double (to 1.536 TB, as 6x 256 GB modules, most likely Toshiba brand as in the PS5 itself), the actual bandwidth performance will very likely remain the same. So, 5.5 GB/s raw bandwidth with compressed typical ranges of 11 GB/s - 12 GB/s, and up to maximum lossy compression range of 17 GB/s - 22 GB/s. This will still be very impressive even at the time of PS5 Pro and provide perfect compatibility with PS5 base, it just wouldn't be the fastest option available anymore. However, considering the investment in ReRAM to make up for this, it's not a bad trade-off.
Regarding main memory, GDDR7 would be the standard. HBM2 would simply be too disruptive as a technological shift to implement in a mid-gen refresh, and still likely carry a price premium compared to GDDR7, while not offering too large a performance benefit (at least in terms of bandwidth; latency would probably be a different conversation) within a price bracket suitable for a mass-market mid-gen console refresh. While it would likely provide lower power consumption, the mid-gen console refreshes would still get more than enough power reduction through other means, to have enough to justify GDDR7 which would, most likely, provide at least SOME power consumption reduction over GDDR6.
For PS5 Pro in particular, Sony would very likely stick with a 256-bit memory bus (they seem to love this bus size ), and they'd want at least some type of increase of GB per TF bandwidth over PS5 base (~ 43 GB/per TF), regardless of how features like Infinity Cache on AMD's RDNA architectures shape out and develop. For those reasons, even if it'd require a slight overclock, it's very possible Sony would go for 20 Gbps GDDR7 modules, as 8x 2 GB modules, for a total of 80 GB/s per module, and a system bandwidth total of 640 GB/s on a 256-bit bus.
Audio would likely be a slight iteration on the Tempest Engine; if possible, it could have some of the SPE-style logic simplified further in order to allow for even easier utilization by developers, and a slight performance increase. Nothing too radical, however; they'd want to ensure it doesn't compete too much in terms of bandwidth with the CPU and especially the GPU. The CPU, as hinted way earlier, would be Zen 5-based; a similar 8 core/16-thread setup as the PS5's Zen 2, with better IPC and not only a unified L3$ cache (which Zen 3 would have already introduced), but some implementation of Infinity Cache on the CPU cache level side as well, this likely being a standard Zen 5 CPU feature however, but nonetheless worth utilizing. The same 3.5 GHz clock of PS5 would be supported, but a clock increase to something like 3.8 GHz or even 4 GHz would not be out of the realm of possibility.
Finally, the GPU. As mentioned before, no 72 CU GPU design here; while a chiplet approach would be supported, we'd see it as 2x 18 CU chiplet blocks. Process-wise, while 3nm (perhaps even 3nm EUV) would be readily available by this time in a general sense, DO keep in mind that costs are NOT scaling down with node shrinks; rather, the opposite is happening i.e prices are INCREASING. With investments already placed in on the ReRAM and (very likely) customizations to any aforementioned features of the GPU chiplet design that don't end up being standard in the RDNA spec by this point, to keep costs down and place investments in other areas Sony would likely go for 5nm EUVL instead, saving 3nm (or 3nm EUV) for a PS6.
It's my personal opinion that the base PS5 is on 7nm EUV. Now, the benefits of 7nm EUV over 7nm DUV (which is what I suspect the Series X is on) are: 17% density gain, and 10% power consumption reduction OR a 10% performance increase, clock-for-clock. Seeing where the PS5 is landing in regards to not just its specs but things that reinforce the perception of certain specs (such as the system's size and cooling solution), I'd say the PS5 may've only gone for half of the possible performance gain benefit of 7nm EUV, so 5%. Some people probably feel differently...some probably would even say it's not 7nm EUV. But I personally feel that to be the case.
With this taken into consideration, a PS5 Pro would see a pure TF performance increase from 10.275 @ 2.23 GHz...to 11.3025 TF @ 2.23 GHz. This, coming with a 30% power consumption reduction thanks to shifting to the 5nm. While 5nm EUVL would provide an additional 10% power consumption reduction, and 5nm itself brings a 30% power consumption reduction, THAT power consumption reduction comes over basic 7nm, and PS5 is already on 7nm EUV and had a 15% power consumption reduction over that. So overall it would come to a 30% power consumption reduction for them on 5nm EUVL instead of 45%.
So picturing all of that, for a 2023 holiday release? Would look rather tempting doesn't it? So let's summarize (semi-TL;DR):
>YEAR: 2023
>NODE: 5nm EUVL
[CPU]
[GPU]
[MEMORY]
[PRICE]
--------------
For Parts 3 and 4, we'll be focusing on Microsoft, who'll have not one, but two big mid-gen refreshes to deal with...
In the meantime, if you have any ideas of what you'd see happening for a PS5 Pro in 2023, share them below and let's talk about it. It's never too early to talk about new hardware
I'm starting with the mid-gen refreshes, one system at a time (originally planned to do all three mid-gen refreshes in one thread, but the write-up grew VERY quickly, so better to give each system its own thread), and then I'll get to the next-next gen stuff. I'm also open to ideas on suggestions with tuning some of these specs, since this needn't be an open-and-shut deal. Seeing that the embargos were finally lifted today, let's start with Sony, and the PlayStation 5 Pro...
----------
In my honest opinion, I think market and technology realities are going to be the driving forces behind what goes into the mid-gen refreshes more than anything. That is to say, I personally think anyone hoping for HBM2, super Big Navi-tier GPU upgrades pushing 20 - 30 TF etc., are in for a massive disappointment in that regard. There are no feasible advances in terms of node shrink reductions, surrounding memory technologies (that would be affordable), or pricing for component R&D and system designs that would enable such mid-gen refreshes being a reality........for the MOST part
Due to this, I'm of the personal opinion that the mid-gen refreshes from Sony and Microsoft will focus on the following main goals:
>Greatly reduce peak power consumption targets
>Notably reduce system physical sizes (this will be a particular goal for Sony with their mid-gen refresh)
>Refine specific technological design concepts and techniques as a testing grounds for what 10th-gen systems could bring
>Improved implementation of Infinity Cache for the L1$ (possibly cut down in terms of full supported cache size
for the consoles however)
>AI dedicated silicon geared towards offloading some aspects of game artificial intelligence models.
>Specific vision processing/sampling silicon baked into the GPU. This could be implemented as a single
core to each Shader Array. Would help with real-time image processing. This is something that can
already be done on the regular GPU shader cores, but specialized silicon for the task that integrates
into the GPU pipeline would do it better, and with lower power consumption.
>Improved image upscaling (silicon budget dedicated to image scaling and upsampling)
>Explore a handful of new technological designs and concepts, which could be iterated on with 10th-gen systems
>Provide modest performance enhancements of 9th-gen game content
>Increase storage baselines
>Keep prices no higher than 9th-gen systems, preferably lower...for the most part
These are the guiding principals I feel are going to drive the mid-gen refreshes from Sony and Microsoft. A bit above I said that there are absolutely some things we SHOULDN'T expect with the mid-gen refreshes. However, I do think it's fair to give a brief mention of at least some of the things that will likely be implemented in them:
>GDDR7, to replace the aging (by 2023) GDDR6
>RDNA 4-based GPU designs, with some RDNA 5 elements custom-built into them. This is assuming a consistent 14-month
period for each RDNA generation step, going off the time span between RDNA 1 and RDNA 2 (14 months). So, RDNA 4 spec and
GPU products would be ready for mass-market by March 2023, and RDNA 5 by May 2024. So you can infer from here timeline
for mid-gen refreshes would range between 2023 and 2024.
>Probably some integration of CDNA 4 features into the GPU designs (likely through extensions of the shaders in the RDNA
silicon, though I can see one of the two (mainly Microsoft) integrate some actual CDNA 4 silicon into their mid-gen refresh)
>At least Zen 5-based CPU designs (following same logic for RDNA generation timings above, Zen 5 would be ready for market
by March 2023)
>At least something chiplet-based (this will most likely be Sony)
>At least some integration of early-stage persistent memory, such as 3D Xpoint or ReRAM (for reasons explained later, this might
more likely be something Sony pursues in particular)
Now then, maybe it's time we move on to giving some system speculations now? Let's go...
[SONY]
Sony's PS5 Pro mid-gen refresh will most likely release in 2023. I see it implementing a chiplet design, not as 2x 36 CU chips, but as 2x 18 CU chiplets, to mimic the base PS5's GPU setup, only without needing four disabled CUs present (on a chiplet design, redundant silicon doesn't need to actually be present on the die). It will be RDNA 4-based, but also take features liberally from the RDNA 5 standard and customize the GPU setup with some of those features. It's very possible Sony would take more from the RDNA 5 spec into their GPU design compared to Microsoft.
Being a chiplet design, we already know the chances are strong that RDNA 3 will be chiplet-based in some capacity. Regardless, I did have my own idea for how a chiplet setup could pan out. On PS5 Pro, each of the two chiplets would feature 18 CUs and 2x 16 ROP/ColorDepth blocks (32 ROPs per chiplet).
To network the two chiplet in tandem, some of the typical GPU logic would need to be split off onto smaller complementary chiplets. One of these would be the "Unifying GPU Chiplet", or UGC for short. The UGC would handle a bevy of things. Chiefly:
>The UGC handles the access routines for the GPUs to main
system memory by having the DMA built into it. The UGC chiplet
block then has Infinity Fabric links at a data rate of 640 GB/s
to the GPU chiplets (links of 320 GB/s to each GPU chiplet), so
they can then work with the data as required.
>There could be a Drawcall Management Block (DMB) on the UGC.
It would be paired as an extension to/of the Command Processor,
and be responsible for automating and managing the processes
for issuance of GPU work to the hardware components of the
chiplets which the Scheduler is mainly responsible for (and
links directly to both chiplets via the IF links that are
mentioned above).
>The Command Processor, and other things such as the Scheduler,
are in this block. The Shader Input blocks are in the chiplets
themselves, one to each chiplet, and both have an independent
connection to this block for data throughput input.
*The Shader Input blocks may need some extra functionality
to provide feedback to the UGC, maybe as a means of some
hardware on the GPU chiplets themselves able to detect
when individual CUs on eiher GPU chiplet is free for more
work to be scheduled to it, that can then communicate
with some silicon on the UGC complimented with the UGC's
Drawcall Management block, to prioritize new work to those
CUs to ensure peak saturation of GPU resources are always
maintained.
>There is also a small block of cache on this block: 256 KB L0$,
1 MB L1$, and 4 MB L2$, for any required pre-processing and
dispatch work, plus any drawcall instructions that can be
saved for later.
>The design of the Unifying GPU chiplet block is that it houses
the traditional GPU components for drawcall instruction sorts
and issues to CUs in the SAs of the SEs, and has its own block of
L2$ that it can share data to the CUs with if required. Each
chiplet's CU has its own L0$, and share an L1$, but there is
no L2$ for the chiplets in the same way as on PS5 base. To
compensate, the shared L1$ size of the CUs is enlarged by 20%
per shared L1$.
The other big complementary GPU chiplet component in the PS5 Pro would be the Unifying Framebuffer Chiplet block, which can be called the UFC for short. This would house the Display block typically seen in AMD GPUs, among some other things, and likely include some various combine modes for dual framebuffers (for the two GPU chiplets) that could selected as presets by developers depending on what type of rendering pipeline they'd wish to utilize for their game. You can think of these various rendering display preset combinations for the dual framebuffers as a mix of the SEGA Saturn's dual framebuffers and the SNES's various Mode settings (such as Mode 7).
The goal here, though, would be to have programming complexity reduced simply to the developer selecting a combination mode for the two framebuffers as long as they understand how the modes function the hardware itself should do the heavy lifting in combining and sorting the stitched outputs depending on what the game wants, and the combination modes should also be able to be switched between 1-2 cycles, to mix combination modes on the needs of what the game needs for optimal output. This is key for allowing maximized use of the framebuffer capabilities, but it also means the UFC needs to have these different framebuffer combination preset modes readily accessible on some type of private local memory. It's best to picture it, then, as an advanced VDP (Video Display Processor); some chunk of NOR flash and embedded SRAM cache in the UFC would be best for this (the NOR flash could store the presets and even allow for XIP (Execute In Place) if desired, while the SRAM would be for fast memory; some hierarchy of L0$, L1$ and L2$ is probably best).
Aside from the aforementioned GPU talk, a PS5 Pro would likely see improved support for PSVR2, with some bump in the Wifi 6 standard. For wired and perhaps wireless dongle-based PSVR connectivity, there could also be a Thuderbolt port provided via supercharging the USB-C port. The last big technological push I could see for a PS5 Pro is inclusion of persistent memory. Sony actually have some patents for ReRAM, which can potentially be used as both a storage-class and DRAM-like class memory technology. By the time a PS5 Pro would be ready, I think Sony would at least have storage-class ReRAM ready. The goal of it would be similar to the role Optane memory serves on compliant desktop PCs; as a bridge between storage-class memory and system RAM.
A block of 32 GB of ReRAM developed in-house (and likely manufactured/fabbed by Sony via TSMC) would be able to provide a notable performance boost to data I/O on a PS5 Pro while having much lower latency than NAND, support for smaller granularity levels in block data sizes, much higher endurance P/E cycles, and more bandwidth compared to even high-class SSDs on the market. While there is currently no commercial ReRAM on the market, there is at least one company with an IP license for storage-class ReRAM providing 25 GB/s of bandwidth. By the time of a PS5 Pro, especially if the ReRA itself had time to mature in the commercial market from 2021 or even 2022 and onward, Sony could possibly have a 24 GB/s - 25 GB/s bandwidth ReRAM solution that could be implemented in a mid-gen refresh at an affordable rate, serving as a great starting ground for similar technology in a PS6.
Due to this, however, I actually DON'T see them doing too much with an SSD I/O spec bump. While the SSD size will likely double (to 1.536 TB, as 6x 256 GB modules, most likely Toshiba brand as in the PS5 itself), the actual bandwidth performance will very likely remain the same. So, 5.5 GB/s raw bandwidth with compressed typical ranges of 11 GB/s - 12 GB/s, and up to maximum lossy compression range of 17 GB/s - 22 GB/s. This will still be very impressive even at the time of PS5 Pro and provide perfect compatibility with PS5 base, it just wouldn't be the fastest option available anymore. However, considering the investment in ReRAM to make up for this, it's not a bad trade-off.
Regarding main memory, GDDR7 would be the standard. HBM2 would simply be too disruptive as a technological shift to implement in a mid-gen refresh, and still likely carry a price premium compared to GDDR7, while not offering too large a performance benefit (at least in terms of bandwidth; latency would probably be a different conversation) within a price bracket suitable for a mass-market mid-gen console refresh. While it would likely provide lower power consumption, the mid-gen console refreshes would still get more than enough power reduction through other means, to have enough to justify GDDR7 which would, most likely, provide at least SOME power consumption reduction over GDDR6.
For PS5 Pro in particular, Sony would very likely stick with a 256-bit memory bus (they seem to love this bus size
), and they'd want at least some type of increase of GB per TF bandwidth over PS5 base (~ 43 GB/per TF), regardless of how features like Infinity Cache on AMD's RDNA architectures shape out and develop. For those reasons, even if it'd require a slight overclock, it's very possible Sony would go for 20 Gbps GDDR7 modules, as 8x 2 GB modules, for a total of 80 GB/s per module, and a system bandwidth total of 640 GB/s on a 256-bit bus.Audio would likely be a slight iteration on the Tempest Engine; if possible, it could have some of the SPE-style logic simplified further in order to allow for even easier utilization by developers, and a slight performance increase. Nothing too radical, however; they'd want to ensure it doesn't compete too much in terms of bandwidth with the CPU and especially the GPU. The CPU, as hinted way earlier, would be Zen 5-based; a similar 8 core/16-thread setup as the PS5's Zen 2, with better IPC and not only a unified L3$ cache (which Zen 3 would have already introduced), but some implementation of Infinity Cache on the CPU cache level side as well, this likely being a standard Zen 5 CPU feature however, but nonetheless worth utilizing. The same 3.5 GHz clock of PS5 would be supported, but a clock increase to something like 3.8 GHz or even 4 GHz would not be out of the realm of possibility.
Finally, the GPU. As mentioned before, no 72 CU GPU design here; while a chiplet approach would be supported, we'd see it as 2x 18 CU chiplet blocks. Process-wise, while 3nm (perhaps even 3nm EUV) would be readily available by this time in a general sense, DO keep in mind that costs are NOT scaling down with node shrinks; rather, the opposite is happening i.e prices are INCREASING. With investments already placed in on the ReRAM and (very likely) customizations to any aforementioned features of the GPU chiplet design that don't end up being standard in the RDNA spec by this point, to keep costs down and place investments in other areas Sony would likely go for 5nm EUVL instead, saving 3nm (or 3nm EUV) for a PS6.
It's my personal opinion that the base PS5 is on 7nm EUV. Now, the benefits of 7nm EUV over 7nm DUV (which is what I suspect the Series X is on) are: 17% density gain, and 10% power consumption reduction OR a 10% performance increase, clock-for-clock. Seeing where the PS5 is landing in regards to not just its specs but things that reinforce the perception of certain specs (such as the system's size and cooling solution), I'd say the PS5 may've only gone for half of the possible performance gain benefit of 7nm EUV, so 5%. Some people probably feel differently...some probably would even say it's not 7nm EUV. But I personally feel that to be the case.
With this taken into consideration, a PS5 Pro would see a pure TF performance increase from 10.275 @ 2.23 GHz...to 11.3025 TF @ 2.23 GHz. This, coming with a 30% power consumption reduction thanks to shifting to the 5nm. While 5nm EUVL would provide an additional 10% power consumption reduction, and 5nm itself brings a 30% power consumption reduction, THAT power consumption reduction comes over basic 7nm, and PS5 is already on 7nm EUV and had a 15% power consumption reduction over that. So overall it would come to a 30% power consumption reduction for them on 5nm EUVL instead of 45%.
So picturing all of that, for a 2023 holiday release? Would look rather tempting doesn't it? So let's summarize (semi-TL;DR):
>YEAR: 2023
>NODE: 5nm EUVL
[CPU]
>GEN: Zen 5 (PC release would be ready by July 2023 going with 16-month timing patterns established so far)
>CLOCK: 3.5 GHz (PS5 Base compat), 4 GHz (default clock for PS5 Enhanced Mode performance)
>CORES: 8
>THREADS: 16
>CACHE:
>L1$: 128 KB
>L2$: 512 KB
**Implements a scaled-down form of Infinity Cache
>L3$: 8 MB
[GPU]
>GEN: RDNA 4 (+ some RDNA 5 features); assumes a 16-month period between generations. RDNA 2 launch Nov. 2020, RDNA 3
launch Mar. 2022, RDNA 4 release July. 2023, RDNA 5 Nov 2024 (PS5 Pro would be one of first RDNA 5-based (in some aspects)
product on market exclusively for 12 months until PC RDNA 5 cards release in May 2024)
>CLOCK: 2.23 GHz
>DESIGN: Chiplet (2x chiplets)
>CUs: 36 (18 per GPU chiplet)
>ROPs: 64 (2x 16 ROP blocks per chiplet)
>ALUs: 2,304
>FEATURES:
>Unifying GPU Chiplet block (UGC)
>Unifying Framebuffer Chiplet block (UFC)
>Improved RT (dedicated RT units built into each Dual CU; the
RT units are linked with adjacent RT units above and below them,
to accelerate RT calculations. Basically, graphics data on
each Dual CU would be broken down to have RT calculations done
for just the shader data that Dual CU is calculating. MOTL)
>Improved AI ML (silicon-level support for GPT 2.0 data models,
though some work would still need to be done on the shaders)
>Improved image upscaling
>TF: 11.3025 TF (2.23 GHz clock)
>POWER CONSUMPTION: 138 watts (average)(106 watts from chiplet design
+ power consumption reduction, + 32 watts for additional GPU hardware
silicon (including larger cache sizes); this is a general wattage estimate, I
have no idea what additional aspects of the GPU would generate what specific
power usage out of this 32 watt figure, the 32 watts would just be the overall
upper limit regardless of the combinations.
>DIE AREA: 94 mm^2 (72 mm^2 from basic die area reduction, + 22 mm^2
from additional GPU hardware; actual die sizes may be larger since
determining mm^2 by wattage per mm^2 is not a 100% method, but a
consistent one for limited estimates)
[MEMORY]
>RAM: 16 GB GDDR7, as 8x 2 GB, 20 Gbps chips @ 640 GB/s (+ 192 GB/s over base PS5)
>PERSISTENT RAM: 32 GB low-level, storage-class ReRAM, 25 GB/s
>STORAGE: 1.536 TB NAND, 5.5 GB/s raw, 11 - 12 GB/s lossless compressed, 17 - 22 GB/s maximum lossy compressed
[PRICE]
>DIGITAL: $299.99
>DISC: $399.99
**Both models will replace their respective base PS5 Digital and PS5 Disc Editions through a gradual phase-
out shift during 2024
--------------
For Parts 3 and 4, we'll be focusing on Microsoft, who'll have not one, but two big mid-gen refreshes to deal with...
In the meantime, if you have any ideas of what you'd see happening for a PS5 Pro in 2023, share them below and let's talk about it. It's never too early to talk about new hardware
Last edited:
