muhammad-abdulla2223.imgbb.com
Yes, and it looks like neither nvidia or amd are eager to sacrifice some diespace for a dedicated hw decompression unit yet since they are both batteling over performance figures. Let's hope the consoles are holding a bright enough candle this gen, that this would change, and we also get some badass dedicated decompression in hw without using up compute power. The best would be if they both backed the same std. so they could have that locked down and be able to focus more on other aspects of the die.
Maybe this? At the top:
Samsung DDR4:
As it usually happens with Samsung’s major DRAM-related announcements, the news today consists of two parts: the first one is about the new DDR4 IC itself, the second part is about the second generation '10 nm-class' (which Samsung calls '1y' nm) manufacturing technology that will be used for other DRAM products by the company. Both parts are important, but let’s start with the new chip.
Or is it just DRAM and they are similarly looking?
This i/o coupled with frustum culling equals MAGICOk, people might get confused by the 22GB/s max. Whether they are raw or compressed, the SSD will send 5.5GB/s. Meaning, after decompression it results in 8-22GB/s inside the APU through the Kraken decompressor then to GPU caches and RAM:
So PCIe 4.0 could only handle 7GB/s, while PS5's SSD would send 5.5GB/s anyway through 4x PCIe 4.0 lanes. When it's inside the I/O complex, it gets decompressed to the original size, ranging from 8-22GB/s.
Hope this explains the concept.
I have no idea what you are talking about captain
I think I should head to the infirmary!
True it was absolutely a 2D system first and foremost, and arguably the last "true" 2D console (as in, having dedicated hardware specifically for 2D tiles and sprite manipulation). But, there's always been some dissenting over how much 3D was an afterthought for SEGA. Based on a few things I'm personally of the POV it wasn't really an afterthought, but the particular level of 3D they eventually got, was something of a last-minute thing.
Consider they not only had their Super-Scaler games in arcades from the mid-80s onwards (that used distorted sprites and was able to scale them quickly to simulate 3D...basically what the Saturn did with distorting quads), and also had their 3D arcade Virtua games by '93, I think that gives some credence to the idea at least Model 1-level 3D was always in the works for Saturn from the planning stages. They always tended to take aspects of their top-line arcade platforms of that era and placed into their home consoles, some things increased, some things stripped down, etc.
It's very hard to picture they would have designed Saturn in the early phases (when it was still called GigaDrive) without any 3D capabilities planned. However, their implementation was probably always going to be quad-based since that's what the arcade division was successful at with the Super-Scaler games (quad texture scaling) and Model 1 (using quadrilaterals for polygons, same thing Saturn would use). I'd probably even say some basic form of texture-mapping was also always in the works for Saturn, since it'd of came out in Japan after the Model 2 came out (IIRC the Model 2 actually put out less polygons than Model 1, but the texture mapping more than made up for it).
If Ken Kutaragi saw a game like Virtua Fighter and used that to convince Sony to commit to the PlayStation, I'm fairly sure the Away Team (the name of the team at SEGA assembled to develop the Saturn) were well enough aware of that game to take its 3D capabilities into the root of Saturn's design, balanced out with beefed-up 2D capabilities. The PS1 specs didn't so much force them to go with 3D, but attempt going with more robust 3D than what they were planning at the time.
Too bad the Away Team didn't have more time to tune the design; I honestly don't think dual processors (or dual VDPs) were necessarily the problem. SEGA's own teams were mastering those kind of setups for years. The problem was they never quite made the setup accessible enough for 3P devs in a gaming world that was quickly transforming, with publishers who needed games done faster (less reliance on assembly language coding). That's why I hope the concept of dual VDPs/dual-GPUs or whatever you want to call it, is perfected with multi-GPU chiplets becoming standard for a new generation of GPUs and consoles.
That's why I'm really interested in Intel's Xe architecture because IMO they're far ahead of AMD and Nvidia in that department. Too bad they've been a node behind them for a long time (and probably for foreseeable future), not even to mention what's been happening on the CPU front, AMD pretty much catching up to them if not surpassing them for the time being. It's gonna be a bit of a long road for Intel to regain their full footing but at least in the GPU space they've got a very strong foundation to work with.
Someone'd need to zoom in and sharpen the image a ton. Probably still wouldn't tell too much.
From what I know on POP (package-on-package) tech, it might be possible the DRAM cache is on top of the FMC, but you'd need some type of laminate substrate. So maybe the wider area is the substrate, but it looks a little too tightly packed between it and where the logic die would be?
Quickly, here's some shots of some POP and what (I guess) you'd usually look for:
Whatever's going on with the FMC in the PS5 shot there, doesn't look like POP.
As to the flash NAND, well the diagram at Road to PS5 did indeed show 12 chips as 12 channels, but the physical layout shot from PS5 teardown seems it only showed 6 chips. Maybe they are MCMs just physically joined to a single 256 GB package but each have their own channel connect direct to the FMC , instead of muxing two channels in the device to a single channel out to the FMC.
Because something like the latter, I think it would probably be drastic enough to require some statement or something we'd (eventually) hear about from a dev; it wouldn't really change performance metrics too much in the grand scheme of things, but it'd be notable enough in any case.
Really nice write-up!True it was absolutely a 2D system first and foremost, and arguably the last "true" 2D console (as in, having dedicated hardware specifically for 2D tiles and sprite manipulation). But, there's always been some dissenting over how much 3D was an afterthought for SEGA. Based on a few things I'm personally of the POV it wasn't really an afterthought, but the particular level of 3D they eventually got, was something of a last-minute thing.
Consider they not only had their Super-Scaler games in arcades from the mid-80s onwards (that used distorted sprites and was able to scale them quickly to simulate 3D...basically what the Saturn did with distorting quads), and also had their 3D arcade Virtua games by '93, I think that gives some credence to the idea at least Model 1-level 3D was always in the works for Saturn from the planning stages. They always tended to take aspects of their top-line arcade platforms of that era and placed into their home consoles, some things increased, some things stripped down, etc.
It's very hard to picture they would have designed Saturn in the early phases (when it was still called GigaDrive) without any 3D capabilities planned. However, their implementation was probably always going to be quad-based since that's what the arcade division was successful at with the Super-Scaler games (quad texture scaling) and Model 1 (using quadrilaterals for polygons, same thing Saturn would use). I'd probably even say some basic form of texture-mapping was also always in the works for Saturn, since it'd of came out in Japan after the Model 2 came out (IIRC the Model 2 actually put out less polygons than Model 1, but the texture mapping more than made up for it).
If Ken Kutaragi saw a game like Virtua Fighter and used that to convince Sony to commit to the PlayStation, I'm fairly sure the Away Team (the name of the team at SEGA assembled to develop the Saturn) were well enough aware of that game to take its 3D capabilities into the root of Saturn's design, balanced out with beefed-up 2D capabilities. The PS1 specs didn't so much force them to go with 3D, but attempt going with more robust 3D than what they were planning at the time.
Too bad the Away Team didn't have more time to tune the design; I honestly don't think dual processors (or dual VDPs) were necessarily the problem. SEGA's own teams were mastering those kind of setups for years. The problem was they never quite made the setup accessible enough for 3P devs in a gaming world that was quickly transforming, with publishers who needed games done faster (less reliance on assembly language coding). That's why I hope the concept of dual VDPs/dual-GPUs or whatever you want to call it, is perfected with multi-GPU chiplets becoming standard for a new generation of GPUs and consoles.
That's why I'm really interested in Intel's Xe architecture because IMO they're far ahead of AMD and Nvidia in that department. Too bad they've been a node behind them for a long time (and probably for foreseeable future), not even to mention what's been happening on the CPU front, AMD pretty much catching up to them if not surpassing them for the time being. It's gonna be a bit of a long road for Intel to regain their full footing but at least in the GPU space they've got a very strong foundation to work with.
Someone'd need to zoom in and sharpen the image a ton. Probably still wouldn't tell too much.
From what I know on POP (package-on-package) tech, it might be possible the DRAM cache is on top of the FMC, but you'd need some type of laminate substrate. So maybe the wider area is the substrate, but it looks a little too tightly packed between it and where the logic die would be?
Quickly, here's some shots of some POP and what (I guess) you'd usually look for:
Whatever's going on with the FMC in the PS5 shot there, doesn't look like POP.
As to the flash NAND, well the diagram at Road to PS5 did indeed show 12 chips as 12 channels, but the physical layout shot from PS5 teardown seems it only showed 6 chips. Maybe they are MCMs just physically joined to a single 256 GB package but each have their own channel connect direct to the FMC , instead of muxing two channels in the device to a single channel out to the FMC.
Because something like the latter, I think it would probably be drastic enough to require some statement or something we'd (eventually) hear about from a dev; it wouldn't really change performance metrics too much in the grand scheme of things, but it'd be notable enough in any case.
To simplify somewhat, the decompression hardware in the PS5 can output decompressed data at a peak rate of 22GB/s, meaning that even if the compression rate was even higher, the hardware itself couldn't "deliver" more than that ~22GB/s (probably a bit less since peak numbers are usually impossible to reach in real-world scenarios)Ok, people might get confused by the 22GB/s max. Whether they are raw or compressed, the SSD will send 5.5GB/s. Meaning, after decompression it results in 8-22GB/s inside the APU through the Kraken decompressor then to GPU caches and RAM:
So PCIe 4.0 could only handle 7GB/s, while PS5's SSD would send 5.5GB/s anyway through 4x PCIe 4.0 lanes. When it's inside the I/O complex, it gets decompressed to the original size, ranging from 8-22GB/s.
Hope this explains the concept.
Maybe this? At the top:
Samsung DDR4:
As it usually happens with Samsung’s major DRAM-related announcements, the news today consists of two parts: the first one is about the new DDR4 IC itself, the second part is about the second generation '10 nm-class' (which Samsung calls '1y' nm) manufacturing technology that will be used for other DRAM products by the company. Both parts are important, but let’s start with the new chip.
Or is it just DRAM and they are similarly looking?
thicc_girls_are_teh_best
said. It looks like its Toshiba 3D TLC NAND. Safe to assume all 6 dies are the same size, and since we know the PS5 is 768 GiB, then each flash chip is 128 GiB (1024 Gb.) And we know it uses 12 channels from the flash to the controller, and 4 lanes of PCIe 4.0 to the SOC.
The PS5 flash controller clearly has a module of DDR4 SDRAM next to it. The 1 TB Samsung 980 Pro M.2 SSD has 1 GB (8 Gb) of Samsung LPDDR4 SDRAM on board for its controller. It looks like the PS5 has the same 1 GB chip, but it could be a different size. Hard to see. I've read that a DRAM cache can help improve read and write speeds. The Samsung 980 Pro 500 GB model only has 4 Gb or 512 MB DDR4, while I think I read the 2 TB model will have 2 GB (16 Gb) of cache. So I'd assume Sony is using 8 Gb.
The PS5 does have 6 flash dies for its SSD as
The Samsung 980 Pro M2 SSD uses just 2 flash chips for its 1 TB model, which are Samsung 3D TLC NAND and 500 GB each, and it likely has 4 or 8 channels, same PCIe Gen4x4, with its own custom controller.
I'm no expert, but isn't the elimination of this small chunk compression stuff one of the things Cerny said had been eliminated in the deep dive? Like it was one of the bottlenecks? Could be wrong~
He never actually said any of that, he just said 12 channels. It doesn't really matter, its a blazing fast SSD in the PS5.
and here i recently just throwing money for "future proof" b550 pcie 4.0 motherboard
i know. it just i expect i could atleast last for 3 years before need to completely change new motherboard. other part like cpu and gpu should not have much issue as long the mobo still somehow supported.
. ). There are obvious differences between SEGA at that time and Sony right now, of course, but the overall main idea is the same: if it comes down to a battle of attrition, Sony loses simply because they have less money and resources to play the shopping game.
That depends if the GPU's cache can effectively be filled up and updated efficiently for it to get as close to its theoretical peak performance. There are a few ways to improve it: (1) Make the cache really big, i.e. Infinity Cache, (2) design a system that only needs to invalidate a portion of the cache instead of evicting the entire cache, or (3) increase the cache bandwidth.
That depends on how much CPU-intensive tasks are offloaded to dedicated, customized hardware. We know for a fact, for instance, that the PS5's decompression chip is more powerful than the XSX's decompression chip in terms of the number of Zen 2 cores offloaded.
That largely depends on the number of CU's that the RAM needs to feed data to. On a memory bandwidth per CU basis, the PS5 actually has an edge over the XSX. On a memory bandwidth per teraflop basis, the XSX has an edge over the PS5 albeit by a much smaller margin. The symmetry of the RAM layout will also affect how effective the RAM bandwidth is. The XSX will inevitably need to access the non-GPU optimized portion of the RAM pool, meaning that it will not be able to sustain the maximum 560 GB/s, especially if RAM usage exceeds 10GB. This will also cause the memory bandwidth per CU and per teraflop numbers to drop.Faster memory bandwidth are now "superficial specs".
www.softwareok.com
I'm seeing some confusion around the chips. The PS5 has 12 chips and one channel per chip correct?
I'm only seeing 6 chips on that board so they are probably stacked. So each chip is actually 2 of them.
There's three on the other side of the board.
I don't know much about this but there's a technology called 3D stacking that can be applied to chips. I'm guessing something similar is happening here.
geordiemp
:Correction:Thanks to
PS5 teardown in depth(Japanese)
https://www.4gamer.net/games/990/G999027/20201016035/
Some intesting point
-Sony used latest CAE technology to design the airflow inside PS5
I don't know. I just thought it sounded a little different from what you were saying when I read it.
LolOodle Kraken + Oodle Texture in action?
Control UE:
PS5: 25GB
XSX: 42GB
Same game, yet 42% smaller.
Control Ultimate Edition PS5 Size Is 42% Smaller Than Xbox Series X Due To Kraken Compression Technique - PlayStation Universe
Control Ultimate Edition PS5 weighs in 42% smaller than the Xbox Series X release thanks to the console's better compression technique.www.psu.com
