Fafalada said:
In all fairness, we don't know yet if the PU runs at same clock speed as the APUs.
Anyway, as you pointed out, the post is very likely to be BS either way.
The APU part is more suspicious... it takes a lot of steroids to change a unti that can only work in co-processor mode like Altivec/VMX and change it into what the patents show us as the APU.
We go from VMX with its three separate sub-units (simple Vector ALU, Complex Vector ALU and Vector permute block) to this:
http://appft1.uspto.gov/netacgi/nph..."International+Business+Machines"+AND+Hofstee
The PU being 64 bits makes the PowerPC 970 come to mind, but then again it sounds a bit wrong to assume that it is the PU...
Even if they were using that core, I'd think that it went under quite serious modifications that made a G5 based dev-kit non-reppresentative of the CELL architecture (in terms of performance, functionality, ISA, compiler and other tools, etc...) quite useless.
As I said, I think that a core based on the PowerPC 970FX (with various modification from IBM in critical and non critical areas) is way too much for a PU (at 2.2 GHz the PowerPC 970FX eats between25-39 Watts alone), but stretching things quite a bit I could almost see it (even though it sounds too much like a wet dream).
I do not see a VMX unit with registers increased from 32x128 bits to 128x128 bits being the APU.
I think that, if the conversation took place, that pairing a hypotetical VMX unit on steroid to the APU was the closest the IBM guy could give the "idea" of what the APU can do in terms of performance without disclosing its internal architecture.