Jeff, why do you keep insisting that dedicated co-processors/DSPs need a separate/dedicated memory controller?
It doesn't work like that. You can only have one memory controller (tied to the GPU) and the memory bandwidth is shared with other processors (CPU, UVD, VCE, TrueAudio DSP etc.) by using internal buses.
Facts; The AMD UVD is a Xtensa accelerator on a ARM AXI bus (Supports Network on Chip) which is managed by a Trustzone processor and that ARM block is connected to the X-86 bus via a Host Guest IOMMU. If you try to process video at the same time you are running a game (video chat) you take memory and memory bus time away from the game.
The host-guest IOMMU connects the ARM bus to the X-86 bus and translates ARM memory requests to the X-86/GPU MMU. In this respect you are correct there is one Memory controller that actually accesses Main memory.
The UVD or Xtensa accelerators are used for video codecs and to comply with TEE (Trusted Execution Environment) recommendations they must have a bus that is Memory managed by a ARM CPU as the Trustzone processor. The player, keys, codecs (Xtensa accelerators) AACS, HDCP, Miracast, Playready porting kit...must also be on that same managed bus.
The PS4 takes the ARM IP out of the APU and moves it to Southbridge
UVD in Southbridge.
Advantages:
1) Video chat, and game recording then take no CPU/GPU/Memory cycles from the APU or GDDR5 memory.
2) Southbridge using DDR3 can support Network standby
3) You get a more secure TEE following all ARM recommendations.
4) Post processing for Video out and pre-processing video in for Gesture/head tracking take no GPU or GDDR5 memory cycles. The same Xtensa accelerators used for codecs are also used for vision processing.
Disadvantage if this is not the case UVD in the APU:
Both video buffer and codec compression occur in the APU and a uncompressed video stream to the HDMI and a codec compressed stream travel down the PCIe to southbridge and Hard Disk data up from Southbridge via the same PCIe and video input for vision processing up through the same PCIe. Additionally one of the VR modes has separate video plus VR distorted 120 FPS going down the PCIe to Southbridge at the same time.
That's 4 video streams down and 2 (stereo remember) video streams up the PCIe bus. Now add video chat while in game and you add another stream up and down the PCIe. With case one where Southbridge contains the ARM video processing only one video stream travels down the PCIe. Vision pre-processing in Southbridge would reduce the two video streams to a depth map which takes 50 % of the bandwidth that 1 video stream needs.
Page 6 ourlines some DRM requirements solved by ARM TEE,
DTCP/IP and HDCP SW and configuration executed in TEE For the PS4, that is the Southbridge as a ARM SoC with Trustzone. This also applies to Miracast support. HDCP =
HDCP 2.2 done in the Southbridge TEE NOT the HDMI chip.
