Ok after reading the blog post, the out of context 7.5GB quote makes more sense
Disclaimer: Im explaining the contents of the post. The accuracy of this info is unknown and would be great if people from the field would chime in
Those two banks of three chips either side of the processor house 2 GB per chip. How does that extra 1 GB get accessed? It can't be accessed at the same time as the first 1 GB because the memory interface is saturated. What happens, instead, is that the memory controller must instead "switch" to the interleaved addressable space covered by those 6x 1 GB portions. This means that, for the 6 GB "slower" memory (in reality, it's not slower but less wide) the memory interface must address that on a separate clock cycle if it wants to be accessed at the full width of the available bus.
From what i understand he claims that memory from the fast & slow pool can't be accessed simultaneously i.e GPU (fast) & CPU (slow) can't access their respective pools simultaneously
The fallout of this can be quite complicated depending on how Microsoft have worked out their memory bus architecture. It could be a complete "switch" whereby on one clock cycle the memory interface uses the interleaved 10 GB portion and on the following clock cycle it accesses the 6 GB portion. This implementation would have the effect of averaging the effective bandwidth for all the memory. If you average this access, you get 392 GB/s for the 10 GB portion and 168 GB/s for the 6 GB portion for a given time frame but individual cycles would be counted at their full bandwidth.
However,
there is another scenario with memory being assigned to each portion based on availability. In this configuration, the memory bandwidth (and access) is dependent on how much RAM is in use.
Below 10 GB, the RAM will always operate at 560 GB/s.
Above 10 GB utilisation, the memory interface must start switching or splitting the access to the memory portions. I don't know if it's technically possible to actually access two different interleaved portions of memory simultaneously by using the two 16-bit channels of the GDDR6 chip but if it were (and
the standard appears to allow for it),
you'd end up with the same memory bandwidths as the "averaged" scenario mentioned above.
He claims than in order to use the full bandwidth total memory use must remain within the 10GB limit including system memory (CPU)
If Microsoft were able to simultaneously access and decouple individual chips from the interleaved portions of memory through their memory controller then you could theoretically push the access to an asymmetric balance, being able to switch between a pure 560 GB/s for 10 GB RAM and a mixed 224 GB/s from 4 GB of that same portion and the full 336 GB/s of the 6 GB portion (also pictured above). This seems unlikely to my understanding of how things work and undesirable from a technical standpoint in terms of game memory access and also architecture design.
In this config bandwidth would be distributed as follows:
6GB @560GB/s
4GB @224GB/s
6GB @336GB/S
Now we can better understand the out of context quote from the article
In comparison, the PS5 has a static 448 GB/s bandwidth for the entire 16 GB of GDDR6 (also operating at 14 GHz, across a 256-bit interface). Yes, the SX has 2.5 GB reserved for system functions and we don't know how much the PS5 reserves for that similar functionality but it doesn't matter - the Xbox SX either has only 7.5 GB of interleaved memory operating at 560 GB/s for game utilisation before it has to start "lowering" the effective bandwidth of the memory below that of the PS5... or the SX has an averaged mixed memory bandwidth that is always below that of the baseline PS4. Either option puts the SX at a disadvantage to the PS5 for more memory intensive games and the latter puts it at a disadvantage all of the time.
He comes to the conclusion that to get the best performance possible out of this configuration all data reads/writes must be limited to the 10GB pool
Now I don't think MS would have designed the system with this limitation just to advertise 560GB/s. They either designed a system (separate buses?) to circumvent this limitation or the info from this post is inaccurate
PS:
sonomamashine
It would be great if you made threads from the source instead of using second hand info from clickbait sites