12 512 GB modules give 768 GB, not 825 GB tho. And again, 12 modules would be 458.3 MB/s each, if speed and bandwidth are the same figure.
Or maybe I should say, from the sounds of it, each channel is 458.3 MB/s, since they are set in parallel. But from what you are saying, each NAND module is slower than that. For example let's say they are 384 MB/s, or 4.6 GB/s across all 12 in parallel. The channels are going to be limited by the NAND module speed, they can't draw data faster than the module itself is configured at silicon level to provide.
If that is the case (and 384 MB/s is a fairer case; the modules could be slower since even 384 MB/s modules are a tad pricey), then the 5.5 GB/s speed spec doesn't actually mean that much. It'd reflect the channel speed in parallel, but the modules aren't providing enough bandwidth to match that rate, and it would make more sense to go by the module rate in parallel.
And if the idea is the XSX's NAND is faster but they are going with less, then the NAND bandwidth in parallel there would actually be quite faster than what the channels can support, by several hundred megabytes, either suggesting they scaled back on the controller or channels, or they are considering changing/upgrading the controller. Or, it's a potentially questionable oversight.
Or if the XSX's NAND is ridiculously overspeced for what the controller can handle, then if the article you reference holds true, PS5's NAND is much slower than expected, and is going to deliver much less than 5.5 GB/s in parallel in practice because, again, the channels can't draw more than what the chips can provide per access/second, from what I'm to understand. But that doesn't sound to be the case from what Cerny said in his presentation.