jeff_rigby
Banned
OnQ123's post after mine and your's make it clear that AMD is going to TSMC to provide for more demand. Edit: From my previous message: Oh as to demand exceeding capacity:
The last few onQ123 posts have been very informative, this video, from a diagram shown in the video, it appears the Fusion Chip shown has CPU, GPU and DDR3 Memory in the same package; all on the same silicon with no 3D stacking is possible but unlikely if just for yield issues. If 3D stacking is being used it's unlikely that APUs will be built with 3D wafer stacking as TSMC has said that they are not supporting standards that allow building from wafers made at other foundries. Regardless, from the last few posts it looks like 3D wafer stacking is less likely. 3D wafer stacked DDR3 memory connected with TSV interposer is still possible.
Edit: See above edit, it appears that putting the posts together the NEW APU Fusion chips with memory are 3D wafer stacked and if demand exceeds the Global foundries FAB in the US and Germany then TSMC using interposer 2.5D will be used. Most likely CPU and GPU are on the same silicon with Memory 3D wafer stacked above it but who knows?
The 2014 and beyond AMD Heterogeneous CPU and Fabric-like computing caused me to do some reading. It's not mentioned by name in the video but that's what was being described. It allows multiple CPUs of the same or different design to run concurrently and share data in a fabric (both hardware and software) that has a common address scheme where concurrency is supported properly with enough cache. It's very complicated and there are various schemes to do this being proposed with one that has become an ISA standard.
The Key as I understand from the video is to provide libraries that make it easy for the programmers, a lesson learned from the Cell which was one of the first heterogeneous CPUs. The idea is different CPU designs have use cases that they excel at but in doing this it makes programming for multiple CPUs very difficult thus the move to OpenCL.
If a FPGA is being included in the PS4, which was mentioned by the Sony CTO but might be for a PS5, it would in some cases be 50 times faster at some functions than the CPU even though running at 1/4 the clock speed. The problem is a FPGA is very difficult to program. Again libraries that make it easier to use a FPGA are needed. (FPGAs are going to reduce in price because of 3D wafer stacking and their use expanded because of both reduced price and new software that make them easier to use.)
onQ123 posts and yours hinge on whether Sony is using off the shelf AMD APU or is building a custom SOC chip. Will it include a FPGA? Sony wants to use the PS4 chip in medical imaging, again mentioned by the Sony CTO. IF it's an off the shelf design they won't have as much advantage.....Software and the Sony name only?
How long has Sony been working on this? Are they thinking as far ahead as they did with the PS3? Is onQ123's post on point...there is support for that as a Sony interview in about 2010 mentioned smaller cycles for game consoles due to the cost in the hardware advances needed to support 10 year cycles. BUT the Sony CTO talked about spending a billion dollars developing the PS4 chipset in the latest post (the PS3 Cell only 400 million and that was shared with IBM and Toshiba)? If off the shelf AMD APU, this is pretty much impossible...... Which do we believe?
