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PlayStation 6 to utilize AMD's 3D stacked chips; AMD UDNA Flagship GPU revived for 2026, Zen 6 Halo with 3D stacking technology, and Zen 6 all on TSMC

Loxus

Member
If it's a choice between HBM and 3D V-cache, V-Cache wins every time.

We're at a point in real-time computing, and especially with the importance of specialized and dense data workloads like ML and raytracing, that data locality is becoming more and more important for GPU performance than ever before.

The costs of moving data around the chip are too prohibitive, and clock speeds can't be pushed much higher because the fabrication technologies are reaching physical limits and diminishing returns on cost.

Designs are starting to look more and more inwards at data locality on die, in order to see architectural improvements that can realise significant performance and efficiency improvements. We're already seeing this with Sony's work on the PS5 Pro registers and cache technologies.

The importance of ML and RT workloads next-gen will make it all the more critical to keep as much data as close to the execution cores as possible. So expanded caches and fat lower-level caches will provide orders of magnitude better performance for the majority of critical GPU workloads next-gen than any benefits HBM will provide to the main memory pool.

3D V-Cache beats HBM on bandwidth and blows it completely out of the water in terms of latency, and latency is the Achilles heel of ML performance. Having greater cache hierarchy performance overall in terms of cache sizes and bandwidth will reduce the pressure on main memory too; meaning Sony can opt for a smaller memory interface width, which reduces die size and complexity, increases yields and thus nets an overall more cost-efficient as well as energy efficient product.
The real question is how much die space Sony is willing to invest in L3 cache.

Wafers aren't exactly cheap to begin with and the process of hybrid bonding 3D V-Cache only adds to the already high wafer cost.

At first with the 3D stacking rumor, I thought it would be 3d V-Cache but that seems too expensive when we're looking at mass production.

Even 3D stacking the CPU/GPU on top of an I/O die doesn't seem viable for mass production at the numbers Sony would want.

I don't think Sony would use 3D stacking for the PS6 at all, maybe fanout design similarly to Strix Halo if there using chiplets.

With the criticality of workloads like ML to next-gen, GPUs are quickly becoming so too.
Best bet for an all round solution is fanout HBM, which isn't much different to how MCD connect to the GPU with RDNA3 or StrixHalo.

You can take a look at this video and decide if you still think the PS6 would use 3D V-Cache.

 
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PaintTinJr

Member
Don't be looking for huge TF numbers with this PS6

Its going to be a lot of AI moving forward
But the two go hand in hand because of the efficient solution they've chosen for the PS5 Pro of making it just another capability of the WGPs. The increased RT or the 300TOPs of the Pro directly correlate to the FLOPs and Half FLOPs, so to go from 300TOPs to 750TOPS, that's going to scale everything else...unless some of the TOPs and RT are inside WGPs as they currently are, and some others on the PS6 are going in an RT engine and NPU with external bridges inside the APU.
 
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FireFly

Member
Well we know the Pro is massively overpriced and not intended to be mass mainstream sold priced product,

The BoM is estimated at $500 on selling 10m and sharing bulk component pricing with OG PS5 and Slim, and the estimate for the Pro's APU is between $180-$230, and RAM estimated is under $70, so I still don't see why they couldn't hit the $750 BoM price for launch with the spec I suggested. a memory budget over $150 and a APU budget around $400 should be enough given the product volumes expected for a OG PS6 IMO.
I make the cost of a Pro APU ~$100 and the PS5 APU ~$50, so if the rest of the console costs $400 to manufacture, you could have 3 x Pro APUs/GPUs for $700 BoM. The GPU tiles wouldn't need a CPU, so would be smaller, but on the other hand that doesn't include the cost of the packaging technology, or the cache you mentioned. Or any other improvements.

Edit: This isn't including the larger Pro SSD in the costing. It is also just the silicon cost paid by AMD and not including AMD's margins.
 
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PaintTinJr

Member
I make the cost of a Pro APU ~$100 and the PS5 APU ~$50, so if the rest of the console costs $400 to manufacture, you could have 3 x Pro APUs/GPUs for $700 BoM. The GPU tiles wouldn't need a CPU, so would be smaller, but on the other hand that doesn't include the cost of the packaging technology, or the cache you mentioned. Or any other improvements.

Edit: This isn't including the larger Pro SSD in the costing. It is also just the silicon cost paid by AMD and not including AMD's margins.
My estimate was that the console items, other than the memory and APU, was just $265, leaving nearly $500 for APU and memory as the volume finished prices to hit a $750 BoM which IMO is the top limit Sony would consider given they'd still maybe need to sub to $600 if sales were PS3 post launch levels.

I agree an expensive 3D cache would look a bit tight on pricing, now but I guess other last level cache options such as re-tasking a much larger IO complex might do, but I still don't see any easy way forward for PlayStation to repeat PS4 Pro to PS5 specs lift with PS5 Pro and PS6 in budget unless it is a multi GPU APU solution.
 

KeplerL2

Member
HBM can still be on the table.
It's not, price per Gb has only increased since Vega launch and that was already sold at a loss.
Who told you HBM increases latency?

HBM is nothing like GDDR in terms of latency, it behaves more like regular DDR.
HBM is very similar to GDDR in latency.
Hey! Considering that 2025 only just started, wouldn't we be looking at a late 2026 release here? Are we even sure that this is PS6 we're talking about?
Thanks.
If it follows PS5 schedule: Q4 2025 A0 tapeout, H1 2026 1st party dev kits, H2 2026 B0 tapeout, H1 2027 3rd party dev kits, H2 2027 launch.
Or they can build a smaller chip (eg. 150 mm^2) with a 128-bit bus and rely on cache.
They can't reduce bus width due to GDDR7 density being 1.5x-2x GDDR6 at best.
If it's a choice between HBM and 3D V-cache, V-Cache wins every time.
Really depends on the workload, AMD cancelled Turin X3D because MI300C (basically Genoa with HBM) was like 10x faster for the workloads that Microsoft was targeting.
 

bitbydeath

Gold Member
They’ll no doubt be looking into speeding up development, be it AI, or other hardware and systems that can reduce the time it takes to make a game.
 
PS6 is design complete and in pre-si validation already, with A0 tapeout scheduled for late this year.
FeWeDsv.jpeg
 
I imagine there will be PS4 games that don't work tho. I also imagine they won't bother with making PSVR2 games work either.
PS4 games will work, as long as the new UDNA GPU supports Wave64 (RDNA supports both Wave64 and Wave32).

CPU shouldn't be an issue thanks to x86-64, even if they switched to Intel (not gonna happen, but anyway).

PSVR2 games should work, as long as PS5 BC works.
 

nial

Gold Member
If it follows PS5 schedule: Q4 2025 A0 tapeout, H1 2026 1st party dev kits, H2 2026 B0 tapeout, H1 2027 3rd party dev kits, H2 2027 launch.
I get it now, thanks.
I was starting to believe a 2028 launch for PS6, but this kinda confirms that Sony is continuing the traditional 7 year lifecycle since PS2.
 
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