The 3MB of L2 cache and 32MB of eDRAM are not rumors. Those come directly from Nintendo target specs and I've confirmed that from multiple spots. Same with the cache being split asymmetrically.
Honestly I would say not to rely that much on how POWER7 looks since its a server chip. Yes it uses eDRAM for L3 cache, but going in more depth of what I said before the PowerPC A2 also uses the same eDRAM for L2 cache. Apparently the idea was to increase the memory on the chip over latency. The idea of L3 cache shouldn't even be thought about for the console as that would just make the die bigger. From what I understand the 32MB is considered as "MEM1". Essentially similar to Wii's 24MB of 1T-SRAM.
Also I don't see how the 3MB of L2 sounds excessive considering Xenon had 1MB and Cell had 2.5MB (if I remember correctly).
I don't dispute that there's going to be a block of 32MB of eDRAM in the console, I just think that it's going to be on-chip with the GPU, like the XBox 360's eDRAM or, as you say, the Wii's 1T-SRAM. The CPU's eDRAM cache is a separate thing, though.
The Power7 is the most appropriate comparison we have. It may be a server processor, and well beyond the power we should expect from the Wii U's CPU, but it's still a general purpose chip, which the A2 is not (it's very explicitly designed as a high-bandwidth network processor, so it doesn't have the same cache requirements).
When I said 3MB of L2 was excessive, I meant if it was used in conjunction with a large amount of L3 cache. If it were the only cache it would be on the low end of my expectations.
SRAM's latency advantage over IBM's 1Mb edram macros diminishes with the increase of overall size - at 8MB (64Mb)
edram already provides better cumulative latency. That said, I don't believe WiiU will feature any substantial CPU-local edram. I think IBM's tech has been aptly used for the needs of the GPU. I think the CPU will 'merely' have a hefty amount of L2 SRAM - asymmetric, as already discussed.
Yes, eDRAM has lower latency in large volumes, so makes sense as a large L3 cache, and SRAM has lower latency in small volumes, so is used as a small L2 cache attached to each core as a low-latency buffer between it and the L3. I'm also not talking about eDRAM just because it's my personal belief that it'll be used, it's about the only thing that IBM have actually
confirmed about the CPU:
IBM said:
The all-new, Power-based microprocessor will pack some of IBM's most advanced technology into an energy-saving silicon package that will power Nintendo's brand new entertainment experience for consumers worldwide. IBM's unique embedded DRAM, for example, is capable of feeding the multi-core processor large chunks of data to make for a smooth entertainment experience.
IBM said:
IBM's embedded dynamic random access memory (test chip shown here) will help deliver a thrilling new game experience to Nintendo fans. The new memory technology, a key element of the new Power microprocessor that IBM is building for the Nintendo Wii U console, can triple the amount of memory contained on a single chip, making for extreme game play.
Extreme gameplay!!!1!
Ahem. My point is that there's going to be eDRAM somewhere on the CPU chip. It doesn't make sense as an off-die cache, both because of the language used above, and the fact that being on-die is what makes IBM's eDRAM "unique". Therefore it makes sense to assume that there's going to be some sort of eDRAM cache on there.
If it is true that there is 3MB of L2 cache, then I see 3 possibilities:
- It's possible that Nintendo and IBM have decided to forego any SRAM and just implement a 3MB L2 eDRAM cache, which I would be somewhat disappointed if they did, given the density that eDRAM is able to achieve.
- It's also possible that they've implemented a 3MB asymmetric L2 SRAM cache, and there's also an L3 eDRAM cache of, say, 6MB, but in that case the 3MB of SRAM would be overkill, and it would be cheaper, denser, and just as efficient to go with as little as 512kB of asymmetric L2 SRAM cache and 8.5MB of L3 eDRAM cache.
- The third possibility is that the L2 cache is eDRAM and there's more L3 eDRAM cache as well. This doesn't really make much sense to me over just having a big pool of L2 eDRAM cache, but I suppose it's possible.
L2 cache is SRAM. I never said anything about there being any eDRAM on the CPU.
Nope, but as you see above, IBM did.
