gt6 is unbalanced I'll give you that, but its doing so much more than other racers from that gen its even pulling some current gen tricks (did you read the df article?). I think Yamauchi's ambition and unwillingness to compromise for the sake of perfection its what made gt6 run below 60 fps. If he was willing to make sacrifices, gt6 would be a better more balanced game but his ambition wants a simSonGoku at best gt6 looks about as good as forza 4, with all fully modeled cars on the track. Then forza runs at locked 60fps. But actually I think environment detail is more inconsistent as well and the cars can sound like lawnmowers. That's it though I'm done shitting on gt now lol.
Not true even need for speed shift on 360 is clearly more detailed than gt6 at its best or forza 4 and its 30fps.
That's just it though, streaming was done to make up for ram deficiencies, we are way past that. It would be more limiting with todays and tomorrows hw
Thanks for the info, so in other words post GCN IS MCM. Whoa i hope this makes it to consoles otherwise we'll be stuck with a puny 10tf card
The latter woulnt need to stream as much.... it could just preload it, that alone puts it on a different level
This is what you are not getting: Streaming is done to overcome memory limitations, what you are saying would apply if you where comparing systems with the same amount of memory but you are not...
SonGoku
yeah, I said shift is 30fps. You said gt6 could pass for a 30fps racer that gen in terms of detail... It can't. Pgr4 is noticeably more detailed than gt6 at its best or forza 4. Gt6 has a few really nice car models but I'm talking overall.
https://research.nvidia.com/sites/default/files/publications/ISCA_2017_MCMGPU.pdf
I said it could pass for a 30fps not the best looking
Obviously sacrifices are made to hit "60 fps"You also said gt6 looks on par with fm4 when using all premium
This has to do with time limitations not hardware
SSD not gonna happen next gen and if the choice is between more ram or ssd, more ram always wins
Oh good! thought you were talking about AMD earlier, so there is hope for a post gcn arch that surpasses the limits
SonGoku
To rephrase my comparison I would say gt6 had the edge in car models in its absolute best case scenario when everything is modeled properly. Quite the uncommon scenario, and then gt6 has noticeably more pop in than forza 4 and worse environment. It's about a draw in terms of what they push in that scenario but forza 4 is locked 60. Maybe gt6 has a tad better AA solution with its mlaa i guess. They could have a decade to work on gt6 and they still couldn't improve the detail beyond what they had in the best case scenario. The ps3 was not some supercomputer like we were told.
Of course it wasn't but its worth noting gt6 has so much going on its pushing some current gen tricks and effects
I said it could pass for a 30fps not the best looking
I also think Yamauchi could off better realized his vision on PS3 if he designed GT6 around locked 30 fps, it would look impressive and feel better than unstable "60 fps"
You also said gt6 looks on par with fm4 when using all premium
This has to do with time limitations not hardware
SSD not gonna happen next gen and if the choice is between more ram or ssd, more ram always wins
I can see them using a 100GB cache built into the motherboard though
Oh good! thought you were talking about AMD earlier, so there is hope for a post gcn arch that surpasses the limits
Btw is he talking about a specific node process related to the 128sm limit? its not very clear
edit: Can't make sense of the math
Assuming linear scaring 256 is 100% faster (or 2x if you will) than 128 SM
The how come he comes to the conclusion that 45.5% speedup is within 10% of a hypothetical 256 sm monolithic gpu
To you guys have an ideia here the famous 3D staked GPU found in Xbox One to understand what onQ123 is saying.
People needs to stop to dream something won't happen.
TSMC’s New Wafer-on-Wafer Process to Empower NVIDIA and AMD GPU Designs
Transistor density scaling is slowing down with Moore's law. This fact coupled with an inability to increase the area of a single GPU die are two crucial points of concern for graphics card manufacturers. And these manufacturers are powering advancements in GPU-based, high-performance computing applications such as artificial intelligence. They are expecting companies like Taiwan Semiconductor Manufacturing Company (TSMC) to increase their rate of innovation to accommodate the rate of innovation provided by Moore's law that is an industry standard.
What is a Multi-Chip Module (MCM) GPU Design?
To increase performance and artificially ensure that the rate of Moore’s law stays constant, package-level integration of multiple GPU modules that leverage high bandwidth and signaling technologies is necessary to increase power efficiency. To partition GPUs into modules (known as GPMs), chip designers have to optimize architecture to decrease latency between bandwidths that bind the stacked GPMs together. They also have to improve the efficacy of GPM data locality. These are just two primary factors motivating design who work toward making these Multi-Chip Module GPUs a convincing insurance policy against the slowing tide of Moore's law.
Since manufacturers like TSMC (Taiwan Semiconductor Manufacturing) have a vested interest as a silicon foundry and chipmaker, they have to ensure that their manufacturing capabilities can continue to scale up GPU performance for big clients like NVIDIA and AMD regardless of industry-wide transistor density scaling slowing down. TSMC recently showed off a promising solution for Wafer-on-Wafer (WoW) technology, which addresses latency between the different GPU clusters that make up an MCM based GPU.
To understand TSMC’s novel WoW innovative approach, the current approach must first be understood. An MCM is generally manufactured using a custom interconnect and an interposer. The interconnect is a bottleneck for the latency between modules in an MCM. Part of the reason for this is that the wafers in an MCM are positioned and connected laterally by the interconnect. And the interconnect is what primarily causes latency between the wafers.
To get around this, TSMC’s new proposal involves the use of Through Silicon Vias (TSVs). These 10-micron holes allow the two silicon wafers to touch. This approach from TSMC is meant to demonstrate that stacking dies on top of one another can improve power efficiency and decrease latency lost between GPMs. (Image courtesy of TSMC.)What is an Interconnect?
The interconnect is one of the most crucial components of consideration when planning, designing, engineering and manufacturing MCMs and integrated circuits like System on a Chip (SoC) or ASIC (Application Specific Integrated Circuit).
Historically, interconnects were built using a wiring approach called subtractive aluminum—where blanket films of aluminum are deposited, patterned then etched—leaving isolated and exposed wires which are then coated in dielectric material. The vias are tiny etching holes, and they interconnect the two wafers to each other through the insulating material. Dynamic Random-Access Memory (DRAM) chips are built this way.
The interconnect layer wiring material has changed in recent years from aluminum to copper. Since the number of transistors that are interconnected on modern microprocessors has increased exponentially, timing delays in the wiring of interconnect levels increased as well, prompting the switch to copper. Copper has a 40 percent less capacitive resistance than aluminum, yielding a 15 percent faster processor speed overall.
Even after switching to the damascene copper manufacturing process, miniaturization of the wires of interconnects produces resistance-capacitance delay issues. Due to the length of the wires increasing while the width decreases, it becomes harder and harder to push electrons through them at the same rate of speed.
The combination of a plateauing rate of transistor scaling and increasing latency between GPMs is part of the reasons why TSMC is using Through-Silicon Vias (TSV) for 3D integration.
What Are the Benefits of TSMC’s Wafer on Wafer Tech for GPUs?
GPUs designed by NVIDIA and AMD and manufactured using TSMC’s wafer-on-wafer technology could become more powerful without increasing their physical size. Layers are stacked vertically rather than horizontally along the printed circuit board (PCB) like solid-state drives (SSDs).
Currently, NVIDIA and AMD GPUs are built from a single wafer, which is why TSMC’s research and development teams completed a goal to stack and bond two wafers, one above the other, on a single package. The single package is a cube-shaped and its two stacked wafers are connected by an electrical interface known as an interposer, which routes each connection to another.
Switching wafer scaling from horizontal to vertical may not seem like the most innovative engineering move of all time, but it is no simple task. The reason it’s going to have an impact on the industry is that TSMC can now offer NVIDIA and AMD the ability to add two GPUs to one graphics card as a “new” or refreshed product offering—without having to develop the architecture of a new GPU to fit more cores. This announcement and plan from TSMC is designed to reduce GPU performance anxiety about the future, as transistor scaling becomes harder to replicate at the exponential rate of years past.
GPU Gains from Wafer-on-Wafer Tech
Since the operating system would detect the twin-wafer GPU stack as one chip instead of a multi-GPU configuration, increasing capacity while using the exact same amount of room as a single card.
Like 3D NAND and DRAM, TSMC should be able to offer NVIDIA and AMD the ability to add more storage capacity, but manufacturing stacking processor wafers will likely prove to be a high-cost endeavor. During inspection, costs could accrue because if one wafer out of the two fails, both must be discarded.
The WoW approach from TSMC is similar to the way the dies are stacked like DRAM and NAND, which allows for faster interfacing and significantly more GPU cores to work with. (Image courtesy of TSMC.)TSMC’s customers include both NVIDIA and AMD, so this wafer-on-wafer stacking process will supposedly ensure that the core count can continue to increase as the technology for transistor scaling slows down industry-wide. It's too early to tell for sure if all the engineering bottlenecks have been addressed.
Won’t Wafer-on-Wafer Be Too Hot?
Mounting the wafers with TSVs leaves more of an air gap between the two wafers. But both components generate heat, which is problematic. The bottom chip’s heat will warm up to top wafer, and though the top wafer will be cooled more than the bottom one. So the heat sink would need to transfer heat away from the small area around the bottom wafer, which is costly to do.
Since WoW is costly, TSMC is likely to use on high-yield production nodes to reduce loss due to waste. But as far as addressing cooling or heating issues, TSMC is pretty mum. The prospect for AMD and NVIDIA to stack dies on top of each other and presto—double the GPU core count for chip refreshes without having to develop new GPU architectures means that GPU-based, high-performance computing applications such as artificial intelligence can continue to rely on historical rates of growth in GPU processing power.
DeepEnigma
I swear not to derail this thread furher after this - but playing pgr3 I didn't think it was any crisper than 4, immediately could tell it's less detailed and more jagged BUT it definitely has a somewhat more colorful aesthetic and glossier cars. You could say pgr4 is a bit more muted. They both have the same motion blur.
Pgr3 looks a bit more like an arcade title i guess, nice looking game overall still!
That's why im confused
Yes but it has to go back ;P
lol true, hopefully its cross gen
If they can pull a PS4 and have 32GB of HBM at 1TB/s (pipe dream) it would be plenty exiting coupled with a 12TF+ GPU
Well they said themselves that they are going with a regular CPU + GPU for their next console. Unless they've changed their mind.
Im curious why 4? I noticed you mentioned it earlier, what makes 4 special? isn't that a bit on the weak side?
I meant your PS5 speculation of 4x18CU
But 4x18CU is really on the weak size, you don't need mcm to reach <8tf.
Regular Ram runs circles around SSD let alone vram, 8GB buffer advantage is massive and wouldn't need to stream as much as the system with lower memory, that's what you are missing entirely
Please provide said examples! Already covered WoW and why it doesn't apply. Games developed around scarce memory use won't be able to take advantage of extra memory so of course streaming has a bigger impact once you met the low memory requirements
PS4 Pro is memory starved, also good thing you have the option to switch drives.
Im sure developers and hardware designers know what's best for the cost to performance ratio. More ram will always win, they won't sacrifice ram or gpu for a ssd drive
No the premium cars had cockpit views except fantasy cars. What you are suggesting has nothing to do with the hardware power to run native res and is just about asset creation. GT Sport is all premium now.
PD became straight trash after gt4 on ps2. I'd actually argue they were only good on ps1.
Well Durango was supposed to be way more powerful than PS4 too.
No they didn't. I've seen ps3 modeled cars without the telltale ps2 textures and jaggies that had no cockpit. Who gives a shit whether it was the hardware or not? The point is PD make an inconsistent unfinished product.
GT Sport is a finished game since day one.
No game have that before internet downloads become a thing lol
Thanks God we have few incomplete games this generations...
I bought titanfall 2 and it kept crashing on startup before I patched it, and Doom ran at 50fps with massive tearing pre patch. With the patch it ran like silk. I can go on.
