Agree.
This rumour also gains validity from the frequency of the XSX GPU. For single threaded performance, frequency and performance is more or less linear. For parallelised work flows you need to have a frequency in mind when designing the silicon. As everyone knows, OCing a GPU gives some gains but it is very uneven. I will make a poor travel analogy from A to B (both routes required):
Route 1 (i.e. parallel workflow 1): 1 km of travel -> 1 hour stop -> 1 km of travel
Route 2: 10 km of travel
So at a speed of 8km/hour the two workflows are equally fast. Increasing the speed by 25% (to 10 km/hour) will in the best case only given you a total increase of 4% due to route 1. However, now the completed tasks in route 2 need to wait for the tasks from route 1, i.e. you start to fill up the cache that can cause other problems so the 4% is your best case scenario.
The analogy is poor but the point is that for parallelised workflow (such as GPU work) the hardware layout design is made with a frequency in mind to keep tasks synchronised per above. Since RDNA2 fab node etc clearly can do higher frequencies from a thermal/power point of view I have wondered why the XSX has the lower frequency since the RDNA2 cards leaked. If the XSX has several RDNA1 transistor layouts for BC reasons, the lower frequency suddenly makes sense.