That's fine I guess. But isn't there some information out there implying that the PS5 is somewhere around 316mm2. If I recall correctly, its the one with the detailed memory configuration leaks (overkill VRM, the chip layout etc.).
Regardless, ~300mm2 for PS5 and ~350mm2 for XSX is the window. That's not a lot of room to play with. The APU by my estimations should be closer to 400mm2. I don't see how 350mm2 is enough for 56CU with RT hardware and the 8 Zen2 cores.
Yea obviously, although I have to make two comments.
1. From Scarlett video, APU calculation (by using memory chips as referrence) seems to be bigger then 350. Closer to 360-370mm² (in line with Xbone and X)
2. Zen2 with 1/4th of L3 cache (as predicted by leaked Flute benchmark and now notebook 8 core Zen 2) is likely smaller then 40mm². So, less then Jaguar with its L3...
I think you can easily fit 40CUs + RT + Zen2 inside 320mm².
Navi 10 with 256bit bus = 251mm²
Zen2 1/4th of L3 cache = ~35-40mm²
RT ~10% for each CU = 10mm²
Audio 3D engine + bus DDR4 = rest
So, easily fits.
What is also interesting is that PCB leak from May not only fits timeline of when chip for dev kit could be released, but also fits in with when V dev kit was released (around June - July for devs).
Also, this leak specified chip size at 22.4 * 14.1mm.
You know what has ~14mm² width? Navi 10 chip. Funny because this was leaked before any Navi was shown or released.