Lagspike_exe
Member
Would be surprised if they managed to get a reasonably sized chip if they did go for N6 again. Perhaps they've done the calculations and found a much bigger N6 chip + additional cooling provisions is still cheaper than a smaller N4P chip.
Thinking about it this could be where Zen 2 and the lower GPU clock come in and start making sense.
If they were going to go with the N5/N4P family then Zen4/4c would make a load more sense, you're already building a distinct, new chip and why would you bother to port Zen 2's topography over to a new process node when Zen 4 already exists on it; and would likely be much easier to integrate and could perform much better at lower clocks?
As for 2180MHz GPU clock, that could suggest a hard limit for the bigger chip (though at that point I'd think it would have made more sense to go down to 54/60CU and get back that extra 53MHz just to simplify BC).
Perhaps it came down to:
N6 + Zen 2 CPU + 2180MHz GPU + heavy cooling = expensive
N5/N4P + Zen 4C CPU + ~2500MHZ GPU + moderate cooling = a little more expensive (due to node cost)
I still think the latter would be more elegant if they could do everything to keep that die as small as possible. Go for a curve ball and drop to a 192-Bit bus but use G6X or the absolute lowest binning GDDR7 cast offs. Keep on-die cache small but stack 3D V-Cache etc. lol As well as of course, 54/60CU rather than 60/64CU (though I'm unsure if the additional Shader Engine logic may offset the die space reduction from 4 less CUs).
Then again, after going through this. The RDNA3 chips this will likely be based on will be on N5 and (and RDNA4 on N4P or N3). So they'll be porting that topography up to N6 which seems like more palaver.
Highly unlikely. They would have to port RDNA 3.5 to N6 for that to work. The power usage of PS5 is already on the high end for a console. Packing the Pro in N6 with a reasonable TDP is not feasible.
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