Geometric-Crusher
"Nintendo games are like indies, and worth at most $19" 🤡
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(Grain of Salt) Moore's Law is Dead: PS6 SoC codenamed 'Orion', PS6 Portable SoC codenamed 'Canis'
Tobimacoss
Member
Keep in mind Magnus is a Chiplet design.
MLiD says the GCD will be used as a desktop GPU with a Media Die attached to it.
Remember that at least AT2 utilizes "Media Dies" chiplet for video output, but also so it can be shared as the iGPU in "Magnus" (and maybe other products?).
I guess they could use the GCD for discrete GPUs. But that Magnus will also need that Media Die for AV1 hardware encoders and decoders in order to be used for xCloud.
Makes sense. If they can match the power draw of Z2X in the Xbox Ally which has 16 CUs, I guess it could work with the chiplet design. Point was, they have to have at least one other configuration.
Something that accommodates 1080/120 and 4k/120 profiles.
I'm not sure if ALL AMD discrete GPUs will have BC. For example, I don't think if an AMD GPU paired up with Intel CPU will have Xbox Console BC.
AMD specifically mentioned "combining the power of Ryzen and Radeon to build a future roadmap". So I think only the AMD APUS or whatever Magnus is categorized as, will have Xbox Console BC.
Even if the GCD portion used in a discrete AMD GPU has the Console BC, it wouldn't function if not paired up AMD Ryzen.
MS is likely going to use Smart Delivery to distribute the GDKX versions of Console libraries to the Xbox platform of devices, regardless of form factor. So it would have to be on select APUs only. Xbox designed, Xbox certified, Xbox branded.
Microsoft’s “Auto Super Resolution” DLSS competitor isn’t exclusive to Qualcomm
It’s not just for specific games, either.
www.theverge.com
Qualcomm Snapdragon X Plus and X Elite devices used Auto SR for upscaling after doing the x64 to ARM64 code translation in real time. Those devices all have NPUs with 50 TOPs.
The leaked Xbox slide also mentioned use of Auto SR. So the NPU will be good enough to do upscaling to at least 1080/60. It's more likely for use on the handhelds and laptops like the Xbox Ally with Z2X includes the NPU.
dgrdsv
Member
Each major step since N7 roughly doubles the price while the advantages in density and clocks on everything past N5 are +50% at best combined.
You're not getting anything out of these new processes aside from the ability to make a huge and expensive as fuck chip - which can only be used in DC space or by Apple since they had like 80% margins on their A chips previously.
N2 is just more of that on top of what we've seen with N7, N5 and N3 already with an added "bonus" in the form of completely lackluster density gains.
I'll be very surprised if next gen consoles will launch on anything but N4. Or, well, they could wait till 2030 I guess.
Moore's Law has slowed down significantly but it's not that bad, N2 is +300% density, +50% fmax and -80% power vs N7 at +200% price.
It's all on N3P.
dgrdsv
Member
LOL no, it +30% at best and will likely be closer to +15% for mixed HP logic and memory. That's against N3P. What's the point in comparing with N7?
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The rumoured price for N5 was ~$17k per wafer, compared with ~$10k for N6/7.
AMD was getting 70% more density for their CPUs with N5, and more for their GPUs (though the setup of RDNA 3 makes it hard to compare). So already you are not seeing an increase in the cost per transistor. And N3 wafers are rumoured to cost ~$18k – ~$20k. For example:
TSMC's wafer pricing now $18,000 for a 3nm wafer
At advanced nodes, chips are not getting cheaper.
If your claim is that N3 wafers instead cost roughly $34k (!), please provide a source.
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Loxus
Member
Media/Display Engines are within the SoC Die.
It would be better to use FSR3 with the Xbox Ally imo. With Magnus though, the GPU being based on RDNA5 is more than capable for upscaling, utilising it's 3rd gen AI Accelerator for FSR5.
Like I said before, the CPU, GPU and NPU all have different use cases.
CPU: Handles complex game logic, physics, open-world simulation, and smarter AI decision-making.
GPU: Renders high-resolution graphics with ray tracing, advanced lighting, detailed effects, and AI-powered upscaling and frame generation.
NPU: Powers real-time NPC speech, dynamic dialogue, adaptive difficulty, real-time gameplay tips, and personalized help based on your playstyle.
pacman4000
Member
Why 192 bit?
"MC" nomally means "Memory Controller" but since a GDDR Memory Controller typically handles 2 channels I suspect "MC" in this case means "Memory Channel".
That gives us 12 memory channels. Each channel is 32 bit giving us a total bus width of 12×32=384 bits.
Or maybe the sketch just sucks...
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Loxus
Member
It's 192-Bit (each MC is 16bit) and 64-128-Bit DDR is speculated to be in the SoC die, like this.
Why 192 bit?
"MC" nomally means "Memory Controller" but since a GDDR Memory Controller typically handle 2 channels I suspect "MC" in this case means "Memory Channel".
That gives us 12 memory channels. Each channel is 32 bit giving us a total bus width of 12×32=384 bits.
Or maybe the sketch just sucks...
Which is a representation I did based on what I think it may look like. As more info becomes available, I'll update it.
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pacman4000
Member
Ohh, I see. "MC" refers to 16 bit sub-channels.It's 192-Bit (each MC is 16bit) and 64-128-Bit DDR is speculated to be in the SoC die, like this.
Which is a representation I did based on what I think it may look like. As more info becomes available, I'll update it.
Very confusing to call them "MC" though. Edit2: And the 4×3 grouping doesn't make any sense either.
Edit: And we are expecting the console to actually use the DDR interface? I.e. we could end up with a 16GB DDR5 + 18GB GDDR7 solution?
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Loxus
Member
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pacman4000
Member
Yeah.Correct.
RTX IO or DirectStorage is how I see it working.
Looking forward to play Excel on this hardware then.
Edit: The good bit is that CPU is no longer handicapped by GDDR latency.
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Proelite
Member
Yeah.
Looking forward to play Excel on this hardware then.
Edit: The good bit is that CPU is no longer handicapped by GDDR latency.
I wonder how much DDR5 is needed to run the OS and legacy Windows games and apps. 16G?
Proelite
Member
It's 192-Bit (each MC is 16bit) and 64-128-Bit DDR is speculated to be in the SoC die, like this.
Which is a representation I did based on what I think it may look like. As more info becomes available, I'll update it.
I think it's most likely dual channel DDR as the CPU die will be in consumer desktop CPUs. Are there even single channel CPUs on the market?
pacman4000
Member
I don't see why there would be parity rules.
As long as the CPU performance and the memory capacity is the same as PS5 the handheld PSP will not cause too much trouble in 99/100 (or so...) games.
That last 1 ambitious (and probably rather costly) game will have to aim for PS6 and higher end PCs (including that xbox) and hope it can make profit despite the more limited pool of potential buyers.
Loxus
Member
The SoC is a custom design and the DDR would most likely be embedded just like how the GDDR7 would be embedded.
It's a unified memory architecture - unless inference has to specifically pass something to a shader, you are just reading/writing the memory same way you would either way.
Worst case you have +1 indirection at the end.
The TOPs need to be in context - this would be targeting 1080p upscales (like Switch 2 for most part) so there's substantially less work to do - and PS5Pro does 4k with 300TOPs, and is getting some version of FSR4 on that.
Proelite
Member
Of course the DDR will be embedded. Doesn't mean the CPU die can't be sold separately as a discrete CPU on the market.
Loxus
Member
We are talking about Magnus right?
Why use the NPU for upscaling, which is on a different die, when the GPU is already more than capable?
Loxus
Member
Pretty sure that would required a new socket.
Maybe I misread, the 50 TOPs NPU part has only been on mobile APUs so far.
In fact 395x already raises that to over 80 IIRC.
But yes Magnus would have the gpu acceleration RDNA4 has, so that's redundant then.
Proelite
Member
Can you explain? You put that die, along with needed extra bits, on a substrate that's BC with current sockets.
i.e. AMD Ryzen 9 9950X is already a MCM.
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pacman4000
Member
Unified architecture with both DDR5 and GDDR7 memory?
Proelite
Member
Well depends on what the DDR5 pool's purpose is. If it's only for OS and legacy Windows games / apps, and new games can use that pool as an L5 cache between GDDR7 and SSD, it's still UMA.
Would depend on the usage and whether or not 18GB of GDDR7 is enough ram for the game, assuming it's 18GB. If it's less than 18GB then UMA in Xbox going forward is dead.
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Physiognomonics
Member
I think the bus spec (192bit) could be a deliberate error in order to track the leaker. 18GB is not enough for next-gen. And I don't believe they are going to go back to PS3 CPU/GPU splitted ram pool.